Subzero: Randomize register assignment.

src/llvm2ice.cpp

 //===- subzero/src/llvm2ice.cpp - Driver for testing ----------------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines a driver that uses LLVM capabilities to parse a
@@ skipping 29 matching lines @@
         clEnumValN(Ice::IceV_InstNumbers, "instnum",
                    "Print instruction numbers"),
         clEnumValN(Ice::IceV_Preds, "pred", "Show predecessors"),
         clEnumValN(Ice::IceV_Succs, "succ", "Show successors"),
         clEnumValN(Ice::IceV_Liveness, "live", "Liveness information"),
         clEnumValN(Ice::IceV_RegManager, "rmgr", "Register manager status"),
         clEnumValN(Ice::IceV_RegOrigins, "orig", "Physical register origins"),
         clEnumValN(Ice::IceV_LinearScan, "regalloc", "Linear scan details"),
         clEnumValN(Ice::IceV_Frame, "frame", "Stack frame layout details"),
         clEnumValN(Ice::IceV_AddrOpt, "addropt", "Address mode optimization"),
+        clEnumValN(Ice::IceV_Random, "random", "Randomization details"),
         clEnumValN(Ice::IceV_All, "all", "Use all verbose options"),
         clEnumValN(Ice::IceV_Most, "most",
                    "Use all verbose options except 'regalloc' and 'time'"),
         clEnumValN(Ice::IceV_None, "none", "No verbosity"), clEnumValEnd));
 static cl::opt<Ice::TargetArch> TargetArch(
     "target", cl::desc("Target architecture:"), cl::init(Ice::Target_X8632),
     cl::values(
         clEnumValN(Ice::Target_X8632, "x8632", "x86-32"),
         clEnumValN(Ice::Target_X8632, "x86-32", "x86-32 (same as x8632)"),
         clEnumValN(Ice::Target_X8632, "x86_32", "x86-32 (same as x8632)"),
@@ skipping 316 matching lines @@
   if (SubzeroTimingEnabled)
     Ctx.dumpTimers();
   if (TimeEachFunction) {
     const bool DumpCumulative = false;
     Ctx.dumpTimers(Ice::GlobalContext::TSK_Funcs, DumpCumulative);
   }
   const bool FinalStats = true;
   Ctx.dumpStats("_FINAL_", FinalStats);
   return GetReturnValue(ErrorStatus);
 }