Subzero: Use CFG-local arena allocation for relevant containers.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 2005 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
   Str << "\tleal\t";
   Operand *Src0 = getSrc(0);
   if (const auto Src0Var = llvm::dyn_cast<Variable>(Src0)) {
     Type Ty = Src0Var->getType();
     // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
     // acceptable type.
-    Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty).emit(Func);
+    Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty)->emit(Func);
   } else {
     Src0->emit(Func);
   }
   Str << ", ";
   getDest()->emit(Func);
 }
 
 template <> void InstX8632Mov::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
@@ skipping 12 matching lines @@
   // safe, we instead widen the dest to match src.  This works even
   // for stack-allocated dest variables because typeWidthOnStack()
   // pads to a 4-byte boundary even if only a lower portion is used.
   // TODO: This assert disallows usages such as copying a floating point
   // value between a vector and a scalar (which movss is used for).
   // Clean this up.
   assert(Func->getTarget()->typeWidthInBytesOnStack(DestTy) ==
          Func->getTarget()->typeWidthInBytesOnStack(SrcTy));
   Src->emit(Func);
   Str << ", ";
-  getDest()->asType(SrcTy).emit(Func);
+  getDest()->asType(SrcTy)->emit(Func);
 }
 
 template <> void InstX8632Mov::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   Type DestTy = Dest->getType();
   Type SrcTy = Src->getType();
   // Mov can be used for GPRs or XMM registers. Also, the type does not
   // necessarily match (Mov can be used for bitcasts). However, when
@@ skipping 369 matching lines @@
       << TypeX8632Attributes[getSrc(0)->getType()].PackString << "\t";
   getSrc(1)->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
   Str << ", ";
   Variable *Dest = getDest();
   // pextrw must take a register dest. There is an SSE4.1 version that takes
   // a memory dest, but we aren't using it. For uniformity, just restrict
   // them all to have a register dest for now.
   assert(Dest->hasReg());
-  Dest->asType(IceType_i32).emit(Func);
+  Dest->asType(IceType_i32)->emit(Func);
 }
 
 template <> void InstX8632Pextr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   const Variable *Dest = getDest();
   Type DispatchTy = Dest->getType();
   assert(DispatchTy == IceType_i16 ||
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
              TargetX8632::SSE4_1);
@@ skipping 22 matching lines @@
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
              >= TargetX8632::SSE4_1);
   Str << "\t" << Opcode
       << TypeX8632Attributes[getDest()->getType()].PackString << "\t";
   getSrc(2)->emit(Func);
   Str << ", ";
   Operand *Src1 = getSrc(1);
   if (const auto Src1Var = llvm::dyn_cast<Variable>(Src1)) {
     // If src1 is a register, it should always be r32.
     if (Src1Var->hasReg()) {
-      Src1Var->asType(IceType_i32).emit(Func);
+      Src1Var->asType(IceType_i32)->emit(Func);
     } else {
       Src1Var->emit(Func);
     }
   } else {
     Src1->emit(Func);
   }
   Str << ", ";
   getDest()->emit(Func);
 }
 
@@ skipping 411 matching lines @@
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice