Subzero: Use llvm::ilist<> for PhiList and AssignList.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 1757 matching lines @@
   //
   // * Stack arguments of vector type are aligned to start at the next
   // highest multiple of 16 bytes.  Other stack arguments are aligned to
   // 4 bytes.
   //
   // This intends to match the section "IA-32 Function Calling
   // Convention" of the document "OS X ABI Function Call Guide" by
   // Apple.
   NeedsStackAlignment = true;
 
+  typedef std::vector<Operand *> OperandList;
   OperandList XmmArgs;
   OperandList StackArgs, StackArgLocations;
   uint32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     Type Ty = Arg->getType();
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
@@ skipping 2353 matching lines @@
   InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs);
   lowerCall(Call);
 }
 
 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to
 // preserve integrity of liveness analysis.  Undef values are also
 // turned into zeroes, since loOperand() and hiOperand() don't expect
 // Undef input.
 void TargetX8632::prelowerPhis() {
   CfgNode *Node = Context.getNode();
-  for (InstPhi *Phi : Node->getPhis()) {
+  for (auto I = Node->getPhis().begin(), E = Node->getPhis().end(); I != E;
+       ++I) {
+    auto Phi = llvm::dyn_cast<InstPhi>(I);
     if (Phi->isDeleted())
       continue;
     Variable *Dest = Phi->getDest();
     if (Dest->getType() == IceType_i64) {
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       InstPhi *PhiLo = InstPhi::create(Func, Phi->getSrcSize(), DestLo);
       InstPhi *PhiHi = InstPhi::create(Func, Phi->getSrcSize(), DestHi);
       for (SizeT I = 0; I < Phi->getSrcSize(); ++I) {
         Operand *Src = Phi->getSrc(I);
@@ skipping 43 matching lines @@
   // available (not live) at the beginning of the successor block,
   // minus all registers used as Dest operands in the Assignments.  To
   // do this, we start off assuming all registers are available, then
   // iterate through the Assignments and remove Dest registers.
   // During this iteration, we also determine whether we will actually
   // need any extra registers for memory-to-memory copies.  If so, we
   // do the actual work of removing the live-in registers from the
   // set.  TODO(stichnot): This work is being repeated for every split
   // edge to the successor, so consider updating LiveIn just once
   // after all the edges are split.
-  for (InstAssign *Assign : Assignments) {
-    Variable *Dest = Assign->getDest();
+  for (auto I = Assignments.begin(), E = Assignments.end(); I != E; ++I) {
+    Variable *Dest = I->getDest();
     if (Dest->hasReg()) {
       Available[Dest->getRegNum()] = false;
-    } else if (isMemoryOperand(Assign->getSrc(0))) {
+    } else if (isMemoryOperand(I->getSrc(0))) {
       NeedsRegs = true; // Src and Dest are both in memory
     }
   }
   if (NeedsRegs) {
     LivenessBV &LiveIn = Func->getLiveness()->getLiveIn(Succ);
     for (int i = LiveIn.find_first(); i != -1; i = LiveIn.find_next(i)) {
       Variable *Var = Func->getLiveness()->getVariable(i, Succ);
       if (Var->hasReg())
         Available[Var->getRegNum()] = false;
     }
   }
   // Iterate backwards through the Assignments.  After lowering each
   // assignment, add Dest to the set of available registers, and
   // remove Src from the set of available registers.  Iteration is
   // done backwards to enable incremental updates of the available
   // register set, and the lowered instruction numbers may be out of
   // order, but that can be worked around by renumbering the block
   // afterwards if necessary.
   for (auto I = Assignments.rbegin(), E = Assignments.rend(); I != E; ++I) {
     Context.rewind();
-    InstAssign *Assign = *I;
+    auto Assign = llvm::dyn_cast<InstAssign>(&*I);
     Variable *Dest = Assign->getDest();
     Operand *Src = Assign->getSrc(0);
     Variable *SrcVar = llvm::dyn_cast<Variable>(Src);
     // Use normal assignment lowering, except lower mem=mem specially
     // so we can register-allocate at the same time.
     if (!isMemoryOperand(Dest) || !isMemoryOperand(Src)) {
       lowerAssign(Assign);
     } else {
       assert(Dest->getType() == Src->getType());
       const llvm::SmallBitVector &RegsForType =
@@ skipping 393 matching lines @@
   } else if (IsConstant || IsExternal)
     Str << "\t.zero\t" << Size << "\n";
   // Size is part of .comm.
 
   if (IsConstant || HasNonzeroInitializer || IsExternal)
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   // Size is part of .comm.
 }
 
 } // end of namespace Ice