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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// | 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file implements the TargetLoweringX8632 class, which | 10 // This file implements the TargetLoweringX8632 class, which |
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1768 // | 1768 // |
1769 // * Stack arguments of vector type are aligned to start at the next | 1769 // * Stack arguments of vector type are aligned to start at the next |
1770 // highest multiple of 16 bytes. Other stack arguments are aligned to | 1770 // highest multiple of 16 bytes. Other stack arguments are aligned to |
1771 // 4 bytes. | 1771 // 4 bytes. |
1772 // | 1772 // |
1773 // This intends to match the section "IA-32 Function Calling | 1773 // This intends to match the section "IA-32 Function Calling |
1774 // Convention" of the document "OS X ABI Function Call Guide" by | 1774 // Convention" of the document "OS X ABI Function Call Guide" by |
1775 // Apple. | 1775 // Apple. |
1776 NeedsStackAlignment = true; | 1776 NeedsStackAlignment = true; |
1777 | 1777 |
| 1778 typedef std::vector<Operand *> OperandList; |
1778 OperandList XmmArgs; | 1779 OperandList XmmArgs; |
1779 OperandList StackArgs, StackArgLocations; | 1780 OperandList StackArgs, StackArgLocations; |
1780 uint32_t ParameterAreaSizeBytes = 0; | 1781 uint32_t ParameterAreaSizeBytes = 0; |
1781 | 1782 |
1782 // Classify each argument operand according to the location where the | 1783 // Classify each argument operand according to the location where the |
1783 // argument is passed. | 1784 // argument is passed. |
1784 for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) { | 1785 for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) { |
1785 Operand *Arg = Instr->getArg(i); | 1786 Operand *Arg = Instr->getArg(i); |
1786 Type Ty = Arg->getType(); | 1787 Type Ty = Arg->getType(); |
1787 // The PNaCl ABI requires the width of arguments to be at least 32 bits. | 1788 // The PNaCl ABI requires the width of arguments to be at least 32 bits. |
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4141 InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs); | 4142 InstCall *Call = makeHelperCall("ice_unreachable", Dest, MaxSrcs); |
4142 lowerCall(Call); | 4143 lowerCall(Call); |
4143 } | 4144 } |
4144 | 4145 |
4145 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to | 4146 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to |
4146 // preserve integrity of liveness analysis. Undef values are also | 4147 // preserve integrity of liveness analysis. Undef values are also |
4147 // turned into zeroes, since loOperand() and hiOperand() don't expect | 4148 // turned into zeroes, since loOperand() and hiOperand() don't expect |
4148 // Undef input. | 4149 // Undef input. |
4149 void TargetX8632::prelowerPhis() { | 4150 void TargetX8632::prelowerPhis() { |
4150 CfgNode *Node = Context.getNode(); | 4151 CfgNode *Node = Context.getNode(); |
4151 for (InstPhi *Phi : Node->getPhis()) { | 4152 for (auto I = Node->getPhis().begin(), E = Node->getPhis().end(); I != E; |
| 4153 ++I) { |
| 4154 auto Phi = llvm::dyn_cast<InstPhi>(I); |
4152 if (Phi->isDeleted()) | 4155 if (Phi->isDeleted()) |
4153 continue; | 4156 continue; |
4154 Variable *Dest = Phi->getDest(); | 4157 Variable *Dest = Phi->getDest(); |
4155 if (Dest->getType() == IceType_i64) { | 4158 if (Dest->getType() == IceType_i64) { |
4156 Variable *DestLo = llvm::cast<Variable>(loOperand(Dest)); | 4159 Variable *DestLo = llvm::cast<Variable>(loOperand(Dest)); |
4157 Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest)); | 4160 Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest)); |
4158 InstPhi *PhiLo = InstPhi::create(Func, Phi->getSrcSize(), DestLo); | 4161 InstPhi *PhiLo = InstPhi::create(Func, Phi->getSrcSize(), DestLo); |
4159 InstPhi *PhiHi = InstPhi::create(Func, Phi->getSrcSize(), DestHi); | 4162 InstPhi *PhiHi = InstPhi::create(Func, Phi->getSrcSize(), DestHi); |
4160 for (SizeT I = 0; I < Phi->getSrcSize(); ++I) { | 4163 for (SizeT I = 0; I < Phi->getSrcSize(); ++I) { |
4161 Operand *Src = Phi->getSrc(I); | 4164 Operand *Src = Phi->getSrc(I); |
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4205 // available (not live) at the beginning of the successor block, | 4208 // available (not live) at the beginning of the successor block, |
4206 // minus all registers used as Dest operands in the Assignments. To | 4209 // minus all registers used as Dest operands in the Assignments. To |
4207 // do this, we start off assuming all registers are available, then | 4210 // do this, we start off assuming all registers are available, then |
4208 // iterate through the Assignments and remove Dest registers. | 4211 // iterate through the Assignments and remove Dest registers. |
4209 // During this iteration, we also determine whether we will actually | 4212 // During this iteration, we also determine whether we will actually |
4210 // need any extra registers for memory-to-memory copies. If so, we | 4213 // need any extra registers for memory-to-memory copies. If so, we |
4211 // do the actual work of removing the live-in registers from the | 4214 // do the actual work of removing the live-in registers from the |
4212 // set. TODO(stichnot): This work is being repeated for every split | 4215 // set. TODO(stichnot): This work is being repeated for every split |
4213 // edge to the successor, so consider updating LiveIn just once | 4216 // edge to the successor, so consider updating LiveIn just once |
4214 // after all the edges are split. | 4217 // after all the edges are split. |
4215 for (InstAssign *Assign : Assignments) { | 4218 for (auto I = Assignments.begin(), E = Assignments.end(); I != E; ++I) { |
4216 Variable *Dest = Assign->getDest(); | 4219 Variable *Dest = I->getDest(); |
4217 if (Dest->hasReg()) { | 4220 if (Dest->hasReg()) { |
4218 Available[Dest->getRegNum()] = false; | 4221 Available[Dest->getRegNum()] = false; |
4219 } else if (isMemoryOperand(Assign->getSrc(0))) { | 4222 } else if (isMemoryOperand(I->getSrc(0))) { |
4220 NeedsRegs = true; // Src and Dest are both in memory | 4223 NeedsRegs = true; // Src and Dest are both in memory |
4221 } | 4224 } |
4222 } | 4225 } |
4223 if (NeedsRegs) { | 4226 if (NeedsRegs) { |
4224 LivenessBV &LiveIn = Func->getLiveness()->getLiveIn(Succ); | 4227 LivenessBV &LiveIn = Func->getLiveness()->getLiveIn(Succ); |
4225 for (int i = LiveIn.find_first(); i != -1; i = LiveIn.find_next(i)) { | 4228 for (int i = LiveIn.find_first(); i != -1; i = LiveIn.find_next(i)) { |
4226 Variable *Var = Func->getLiveness()->getVariable(i, Succ); | 4229 Variable *Var = Func->getLiveness()->getVariable(i, Succ); |
4227 if (Var->hasReg()) | 4230 if (Var->hasReg()) |
4228 Available[Var->getRegNum()] = false; | 4231 Available[Var->getRegNum()] = false; |
4229 } | 4232 } |
4230 } | 4233 } |
4231 // Iterate backwards through the Assignments. After lowering each | 4234 // Iterate backwards through the Assignments. After lowering each |
4232 // assignment, add Dest to the set of available registers, and | 4235 // assignment, add Dest to the set of available registers, and |
4233 // remove Src from the set of available registers. Iteration is | 4236 // remove Src from the set of available registers. Iteration is |
4234 // done backwards to enable incremental updates of the available | 4237 // done backwards to enable incremental updates of the available |
4235 // register set, and the lowered instruction numbers may be out of | 4238 // register set, and the lowered instruction numbers may be out of |
4236 // order, but that can be worked around by renumbering the block | 4239 // order, but that can be worked around by renumbering the block |
4237 // afterwards if necessary. | 4240 // afterwards if necessary. |
4238 for (auto I = Assignments.rbegin(), E = Assignments.rend(); I != E; ++I) { | 4241 for (auto I = Assignments.rbegin(), E = Assignments.rend(); I != E; ++I) { |
4239 Context.rewind(); | 4242 Context.rewind(); |
4240 InstAssign *Assign = *I; | 4243 auto Assign = llvm::dyn_cast<InstAssign>(&*I); |
4241 Variable *Dest = Assign->getDest(); | 4244 Variable *Dest = Assign->getDest(); |
4242 Operand *Src = Assign->getSrc(0); | 4245 Operand *Src = Assign->getSrc(0); |
4243 Variable *SrcVar = llvm::dyn_cast<Variable>(Src); | 4246 Variable *SrcVar = llvm::dyn_cast<Variable>(Src); |
4244 // Use normal assignment lowering, except lower mem=mem specially | 4247 // Use normal assignment lowering, except lower mem=mem specially |
4245 // so we can register-allocate at the same time. | 4248 // so we can register-allocate at the same time. |
4246 if (!isMemoryOperand(Dest) || !isMemoryOperand(Src)) { | 4249 if (!isMemoryOperand(Dest) || !isMemoryOperand(Src)) { |
4247 lowerAssign(Assign); | 4250 lowerAssign(Assign); |
4248 } else { | 4251 } else { |
4249 assert(Dest->getType() == Src->getType()); | 4252 assert(Dest->getType() == Src->getType()); |
4250 const llvm::SmallBitVector &RegsForType = | 4253 const llvm::SmallBitVector &RegsForType = |
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4644 } else if (IsConstant || IsExternal) | 4647 } else if (IsConstant || IsExternal) |
4645 Str << "\t.zero\t" << Size << "\n"; | 4648 Str << "\t.zero\t" << Size << "\n"; |
4646 // Size is part of .comm. | 4649 // Size is part of .comm. |
4647 | 4650 |
4648 if (IsConstant || HasNonzeroInitializer || IsExternal) | 4651 if (IsConstant || HasNonzeroInitializer || IsExternal) |
4649 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; | 4652 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; |
4650 // Size is part of .comm. | 4653 // Size is part of .comm. |
4651 } | 4654 } |
4652 | 4655 |
4653 } // end of namespace Ice | 4656 } // end of namespace Ice |
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