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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 791473003: MIPS: Enable Math rounding operations call reduction optimization in TF. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Addressed comments. Created 6 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 35 matching lines...) Expand 10 before | Expand all | Expand 10 after
46 V(Mips64Tst32) \ 46 V(Mips64Tst32) \
47 V(Mips64Cmp) \ 47 V(Mips64Cmp) \
48 V(Mips64Cmp32) \ 48 V(Mips64Cmp32) \
49 V(Mips64CmpD) \ 49 V(Mips64CmpD) \
50 V(Mips64AddD) \ 50 V(Mips64AddD) \
51 V(Mips64SubD) \ 51 V(Mips64SubD) \
52 V(Mips64MulD) \ 52 V(Mips64MulD) \
53 V(Mips64DivD) \ 53 V(Mips64DivD) \
54 V(Mips64ModD) \ 54 V(Mips64ModD) \
55 V(Mips64SqrtD) \ 55 V(Mips64SqrtD) \
56 V(Mips64FloorD) \ 56 V(Mips64Float64Floor) \
57 V(Mips64CeilD) \ 57 V(Mips64Float64Ceil) \
58 V(Mips64RoundTruncateD) \ 58 V(Mips64Float64RoundTruncate) \
59 V(Mips64CvtSD) \ 59 V(Mips64CvtSD) \
60 V(Mips64CvtDS) \ 60 V(Mips64CvtDS) \
61 V(Mips64TruncWD) \ 61 V(Mips64TruncWD) \
62 V(Mips64TruncUwD) \ 62 V(Mips64TruncUwD) \
63 V(Mips64CvtDW) \ 63 V(Mips64CvtDW) \
64 V(Mips64CvtDUw) \ 64 V(Mips64CvtDUw) \
65 V(Mips64Lb) \ 65 V(Mips64Lb) \
66 V(Mips64Lbu) \ 66 V(Mips64Lbu) \
67 V(Mips64Sb) \ 67 V(Mips64Sb) \
68 V(Mips64Lh) \ 68 V(Mips64Lh) \
(...skipping 30 matching lines...) Expand all
99 #define TARGET_ADDRESSING_MODE_LIST(V) \ 99 #define TARGET_ADDRESSING_MODE_LIST(V) \
100 V(MRI) /* [%r0 + K] */ \ 100 V(MRI) /* [%r0 + K] */ \
101 V(MRR) /* [%r0 + %r1] */ 101 V(MRR) /* [%r0 + %r1] */
102 102
103 103
104 } // namespace compiler 104 } // namespace compiler
105 } // namespace internal 105 } // namespace internal
106 } // namespace v8 106 } // namespace v8
107 107
108 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 108 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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