Add support for acquire, release, and acq_rel memory ordering in PNaCl

test/Transforms/NaCl/atomic/atomic_others.ll

Index: test/Transforms/NaCl/atomic/atomic_others.ll
diff --git a/test/Transforms/NaCl/atomic/atomic_others.ll b/test/Transforms/NaCl/atomic/atomic_others.ll
index efc834b3db8502085f37135fbcd0d9ac29e52f5a..9ca90b6a996eb3e072f4276f5f5873bc5b6eec02 100644
--- a/test/Transforms/NaCl/atomic/atomic_others.ll
+++ b/test/Transforms/NaCl/atomic/atomic_others.ll
@@ -1,8 +1,9 @@
 ; RUN: opt -nacl-rewrite-atomics -S < %s | FileCheck %s
 ;
-; Validate that atomic non-sequentially consistent loads/stores get rewritten
-; into NaCl atomic builtins with sequentially consistent memory ordering (enum
-; value 6). This will change once we support other memory orderings.

[Jim Stichnoth, 2015/01/07 21:21:01]

Should there be a "this may change..." comment left in, or is this pretty much
the final set of consistency options we are going to support?

[JF, 2015/01/07 21:33:57]

I'm not sure when/how it'll change: consume will likely be renamed to something
else (in which case it's a new memory ordering) and the verdict is still out on
relaxed. I'd rather not explain the subtleties here.

This CL's change was exactly as intended when the comment was written, but the
future changes are pretty unknown.

+; Validate that atomic non-{acquire/release/acq_rel/seq_cst} loads/stores get
+; rewritten into NaCl atomic builtins with sequentially consistent memory
+; ordering (enum value 6), and that acquire/release/acq_rel remain as-is (enum
+; values 3/4/5).
 ;
 ; Note that monotonic doesn't exist in C11/C++11, and consume isn't implemented
 ; in LLVM yet.
@@ -39,21 +40,21 @@ define void @test_atomic_store_unordered_i32(i32* %ptr, i32 %value) {
 
 ; CHECK-LABEL: @test_atomic_load_acquire_i32
 define i32 @test_atomic_load_acquire_i32(i32* %ptr) {
-  ; CHECK-NEXT: %res = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
+  ; CHECK-NEXT: %res = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 3)
   %res = load atomic i32* %ptr acquire, align 4
   ret i32 %res  ; CHECK-NEXT: ret i32 %res
 }
 
 ; CHECK-LABEL: @test_atomic_store_release_i32
 define void @test_atomic_store_release_i32(i32* %ptr, i32 %value) {
-  ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i32(i32 %value, i32* %ptr, i32 6)
+  ; CHECK-NEXT: call void @llvm.nacl.atomic.store.i32(i32 %value, i32* %ptr, i32 4)
   store atomic i32 %value, i32* %ptr release, align 4
   ret void  ; CHECK-NEXT: ret void
 }
 
 ; CHECK: @test_fetch_and_add_i32
 define i32 @test_fetch_and_add_i32(i32* %ptr, i32 %value) {
-  ; CHECK-NEXT: %res = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %value, i32 6)
+  ; CHECK-NEXT: %res = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %value, i32 5)
   %res = atomicrmw add i32* %ptr, i32 %value acq_rel
   ret i32 %res  ; CHECK-NEXT: ret i32 %res
 }