Add support for acquire, release, and acq_rel memory ordering in PNaCl

lib/Transforms/NaCl/RewriteAtomics.cpp

 //===- RewriteAtomics.cpp - Stabilize instructions used for concurrency ---===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass encodes atomics, volatiles and fences using NaCl intrinsics
@@ skipping 70 matching lines @@
   AtomicVisitor() LLVM_DELETED_FUNCTION;
   AtomicVisitor(const AtomicVisitor &) LLVM_DELETED_FUNCTION;
   AtomicVisitor &operator=(const AtomicVisitor &) LLVM_DELETED_FUNCTION;
 
   /// Create an integer constant holding a NaCl::MemoryOrder that can be
   /// passed as an argument to one of the @llvm.nacl.atomic.*
   /// intrinsics. This function may strengthen the ordering initially
   /// specified by the instruction \p I for stability purpose.
   template <class Instruction>
   ConstantInt *freezeMemoryOrder(const Instruction &I, AtomicOrdering O) const;
+  std::pair<ConstantInt *, ConstantInt *>
+  freezeMemoryOrder(const AtomicCmpXchgInst &I, AtomicOrdering S,
+                    AtomicOrdering F) const;
 
   /// Sanity-check that instruction \p I which has pointer and value
   /// parameters have matching sizes \p BitSize for the type-pointed-to
   /// and the value's type \p T.
   void checkSizeMatchesType(const Instruction &I, unsigned BitSize,
                             const Type *T) const;
 
   /// Verify that loads and stores are at least naturally aligned. Use
   /// byte alignment because converting to bits could truncate the
   /// value.
@@ skipping 69 matching lines @@
   if (const LoadInst *L = dyn_cast<LoadInst>(&I)) {
     if (L->isVolatile())
       AO = NaCl::MemoryOrderSequentiallyConsistent;
   } else if (const StoreInst *S = dyn_cast<StoreInst>(&I)) {
     if (S->isVolatile())
       AO = NaCl::MemoryOrderSequentiallyConsistent;
   }
 
   if (AO == NaCl::MemoryOrderInvalid) {
     switch (O) {
-    default:
     case NotAtomic: llvm_unreachable("unexpected memory order");
     // Monotonic is a strict superset of Unordered. Both can therefore
     // map to Relaxed ordering, which is in the C11/C++11 standard.
     case Unordered: AO = NaCl::MemoryOrderRelaxed; break;
     case Monotonic: AO = NaCl::MemoryOrderRelaxed; break;
     // TODO Consume is currently unspecified by LLVM's internal IR.
     case Acquire: AO = NaCl::MemoryOrderAcquire; break;
     case Release: AO = NaCl::MemoryOrderRelease; break;
     case AcquireRelease: AO = NaCl::MemoryOrderAcquireRelease; break;
     case SequentiallyConsistent:
       AO = NaCl::MemoryOrderSequentiallyConsistent; break;
     }
   }
 
-  // TODO For now only sequential consistency is allowed.
-  AO = NaCl::MemoryOrderSequentiallyConsistent;
+  // TODO For now only acquire/release/acq_rel/seq_cst are allowed.
+  if (AO == NaCl::MemoryOrderRelaxed)
+    AO = NaCl::MemoryOrderSequentiallyConsistent;
 
   return ConstantInt::get(Type::getInt32Ty(C), AO);
 }
 
+std::pair<ConstantInt *, ConstantInt *>
+AtomicVisitor::freezeMemoryOrder(const AtomicCmpXchgInst &I, AtomicOrdering S,
+                                 AtomicOrdering F) const {
+  if (S == Release)
+    // According to C++11's [atomics.types.operations.req], cmpxchg with release
+    // success memory ordering must have relaxed failure memory ordering, which
+    // PNaCl currently disallows. Change it to the next-strongest ordering.
+    S = AcquireRelease;
+  if (F == Unordered || F == Monotonic) // Both are treated as relaxed.
+    F = AtomicCmpXchgInst::getStrongestFailureOrdering(S);
+  return std::make_pair(freezeMemoryOrder(I, S), freezeMemoryOrder(I, F));
+}
+
 void AtomicVisitor::checkSizeMatchesType(const Instruction &I, unsigned BitSize,
                                          const Type *T) const {
   Type *IntType = Type::getIntNTy(C, BitSize);
   if (IntType && T == IntType)
     return;
   report_fatal_error("unsupported atomic type " + ToStr(*T) + " of size " +
                      Twine(BitSize) + " bits in: " + ToStr(I));
 }
 
 void AtomicVisitor::checkAlignment(const Instruction &I, unsigned ByteAlignment,
@@ skipping 141 matching lines @@
 ///       %object, %expected, %desired, memory_order_success,
 ///       memory_order_failure)
 ///   %success = icmp eq %old, %val
 /// Note: weak is currently dropped if present, the cmpxchg is always strong.
 void AtomicVisitor::visitAtomicCmpXchgInst(AtomicCmpXchgInst &I) {
   PointerHelper<AtomicCmpXchgInst> PH(*this, I);
   const NaCl::AtomicIntrinsics::AtomicIntrinsic *Intrinsic =
       findAtomicIntrinsic(I, Intrinsic::nacl_atomic_cmpxchg, PH.PET);
   checkSizeMatchesType(I, PH.BitSize, I.getCompareOperand()->getType());
   checkSizeMatchesType(I, PH.BitSize, I.getNewValOperand()->getType());
+  auto Order =
+      freezeMemoryOrder(I, I.getSuccessOrdering(), I.getFailureOrdering());
   Value *Args[] = {PH.P, I.getCompareOperand(), I.getNewValOperand(),
-                   freezeMemoryOrder(I, I.getSuccessOrdering()),
-                   freezeMemoryOrder(I, I.getFailureOrdering())};
+                   Order.first, Order.second};
   replaceInstructionWithIntrinsicCall(I, Intrinsic, PH.OriginalPET, PH.PET,
                                       Args);
 }
 
 ///   fence memory_order
 /// becomes:
 ///   call void @llvm.nacl.atomic.fence(memory_order)
 /// and
 ///   call void asm sideeffect "", "~{memory}"()
 ///   fence seq_cst
@@ skipping 22 matching lines @@
                                         ArrayRef<Value *>());
   } else {
     const NaCl::AtomicIntrinsics::AtomicIntrinsic *Intrinsic =
         findAtomicIntrinsic(I, Intrinsic::nacl_atomic_fence, T);
     Value *Args[] = {freezeMemoryOrder(I, I.getOrdering())};
     replaceInstructionWithIntrinsicCall(I, Intrinsic, T, T, Args);
   }
 }
 
 ModulePass *llvm::createRewriteAtomicsPass() { return new RewriteAtomics(); }