Process two 32-bit digits as one 64-bit digit in all bigint intrinsics on x64.

runtime/vm/assembler_x64.cc

Index: runtime/vm/assembler_x64.cc
===================================================================
--- runtime/vm/assembler_x64.cc	(revision 42579)
+++ runtime/vm/assembler_x64.cc	(working copy)
@@ -2049,6 +2049,14 @@
 }
 
 
+void Assembler::divq(Register reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitRegisterREX(reg, REX_W);
+  EmitUint8(0xF7);
+  EmitOperand(6, Operand(reg));
+}
+
+
 void Assembler::imull(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
@@ -2122,6 +2130,14 @@
 }
 
 
+void Assembler::mulq(Register reg) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  EmitRegisterREX(reg, REX_W);
+  EmitUint8(0xF7);
+  EmitOperand(4, Operand(reg));
+}
+
+
 void Assembler::subq(Register dst, Register src) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(src);
@@ -2272,6 +2288,18 @@
 }
 
 
+void Assembler::shldq(Register dst, Register src, const Immediate& imm) {
+  AssemblerBuffer::EnsureCapacity ensured(&buffer_);
+  ASSERT(imm.is_int8());
+  Operand operand(src);
+  EmitOperandREX(dst, operand, REX_W);
+  EmitUint8(0x0F);
+  EmitUint8(0xA4);
+  EmitOperand(src & 7, Operand(dst));
+  EmitUint8(imm.value() & 0xFF);
+}
+
+
 void Assembler::incl(const Address& address) {
   AssemblerBuffer::EnsureCapacity ensured(&buffer_);
   Operand operand(address);