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Issue 786933009: Process two 32-bit digits as one 64-bit digit in all bigint intrinsics on x64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 5 years, 11 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_X64_H_ 5 #ifndef VM_ASSEMBLER_X64_H_
6 #define VM_ASSEMBLER_X64_H_ 6 #define VM_ASSEMBLER_X64_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_x64.h directly; use assembler.h instead. 9 #error Do not include assembler_x64.h directly; use assembler.h instead.
10 #endif 10 #endif
(...skipping 552 matching lines...) Expand 10 before | Expand all | Expand 10 after
563 void adcq(Register dst, const Immediate& imm); 563 void adcq(Register dst, const Immediate& imm);
564 void adcq(Register dst, const Address& address); 564 void adcq(Register dst, const Address& address);
565 565
566 void cdq(); 566 void cdq();
567 void cqo(); 567 void cqo();
568 568
569 void idivl(Register reg); 569 void idivl(Register reg);
570 void divl(Register reg); 570 void divl(Register reg);
571 571
572 void idivq(Register reg); 572 void idivq(Register reg);
573 void divq(Register reg);
573 574
574 void imull(Register dst, Register src); 575 void imull(Register dst, Register src);
575 void imull(Register reg, const Immediate& imm); 576 void imull(Register reg, const Immediate& imm);
576 void mull(Register reg); 577 void mull(Register reg);
577 578
578 void imulq(Register dst, Register src); 579 void imulq(Register dst, Register src);
579 void imulq(Register dst, const Address& address); 580 void imulq(Register dst, const Address& address);
580 void imulq(Register dst, const Immediate& imm); 581 void imulq(Register dst, const Immediate& imm);
581 void MulImmediate(Register reg, const Immediate& imm, Register pp); 582 void MulImmediate(Register reg, const Immediate& imm, Register pp);
583 void mulq(Register reg);
582 584
583 void subl(Register dst, Register src); 585 void subl(Register dst, Register src);
584 void subl(Register dst, const Immediate& imm); 586 void subl(Register dst, const Immediate& imm);
585 void subl(Register dst, const Address& address); 587 void subl(Register dst, const Address& address);
586 void sbbl(Register dst, Register src); 588 void sbbl(Register dst, Register src);
587 void sbbl(Register dst, const Immediate& imm); 589 void sbbl(Register dst, const Immediate& imm);
588 void sbbl(Register dst, const Address& address); 590 void sbbl(Register dst, const Address& address);
589 591
590 void subq(Register dst, Register src); 592 void subq(Register dst, Register src);
591 void subq(Register reg, const Immediate& imm); 593 void subq(Register reg, const Immediate& imm);
(...skipping 11 matching lines...) Expand all
603 void sarl(Register reg, const Immediate& imm); 605 void sarl(Register reg, const Immediate& imm);
604 void sarl(Register operand, Register shifter); 606 void sarl(Register operand, Register shifter);
605 void shldl(Register dst, Register src, const Immediate& imm); 607 void shldl(Register dst, Register src, const Immediate& imm);
606 608
607 void shlq(Register reg, const Immediate& imm); 609 void shlq(Register reg, const Immediate& imm);
608 void shlq(Register operand, Register shifter); 610 void shlq(Register operand, Register shifter);
609 void shrq(Register reg, const Immediate& imm); 611 void shrq(Register reg, const Immediate& imm);
610 void shrq(Register operand, Register shifter); 612 void shrq(Register operand, Register shifter);
611 void sarq(Register reg, const Immediate& imm); 613 void sarq(Register reg, const Immediate& imm);
612 void sarq(Register operand, Register shifter); 614 void sarq(Register operand, Register shifter);
615 void shldq(Register dst, Register src, const Immediate& imm);
613 616
614 void incl(const Address& address); 617 void incl(const Address& address);
615 void decl(const Address& address); 618 void decl(const Address& address);
616 619
617 void incq(Register reg); 620 void incq(Register reg);
618 void incq(const Address& address); 621 void incq(const Address& address);
619 void decq(Register reg); 622 void decq(Register reg);
620 void decq(const Address& address); 623 void decq(const Address& address);
621 624
622 void negl(Register reg); 625 void negl(Register reg);
(...skipping 571 matching lines...) Expand 10 before | Expand all | Expand 10 after
1194 } 1197 }
1195 1198
1196 1199
1197 inline void Assembler::EmitOperandSizeOverride() { 1200 inline void Assembler::EmitOperandSizeOverride() {
1198 EmitUint8(0x66); 1201 EmitUint8(0x66);
1199 } 1202 }
1200 1203
1201 } // namespace dart 1204 } // namespace dart
1202 1205
1203 #endif // VM_ASSEMBLER_X64_H_ 1206 #endif // VM_ASSEMBLER_X64_H_
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