Merge bleeding edge up to 9192 into the GC branch.

test/cctest/test-assembler-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 756 matching lines @@
     int32_t long_hi;
     int32_t long_lo;
     int32_t b_long_hi;
     int32_t b_long_lo;
   } T;
   T t;
 
   Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
-  if (CpuFeatures::IsSupported(FPU)) {
+  if (CpuFeatures::IsSupported(FPU) && mips32r2) {
     CpuFeatures::Scope scope(FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
 
     // Save the raw bits of the double.
     __ mfc1(t0, f0);
     __ mfc1(t1, f1);
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, dbl_mant)));
     __ sw(t1, MemOperand(a0, OFFSET_OF(T, dbl_exp)));
@@ skipping 464 matching lines @@
   CHECK(GET_FPU_ERR(t.type##_err4_out) & kFCSRInvalidOpFlagMask); \
   CHECK_EQ(kFPUInvalidResult, t.type##_invalid_result);
 
     CHECK_ROUND_RESULT(round);
     CHECK_ROUND_RESULT(floor);
     CHECK_ROUND_RESULT(ceil);
     CHECK_ROUND_RESULT(cvt);
   }
 }
 
+
+TEST(MIPS15) {
+  // Test chaining of label usages within instructions (issue 1644).
+  InitializeVM();
+  v8::HandleScope scope;
+  Assembler assm(Isolate::Current(), NULL, 0);
+
+  Label target;
+  __ beq(v0, v1, &target);
+  __ nop();
+  __ bne(v0, v1, &target);
+  __ nop();
+  __ bind(&target);
+  __ nop();
+}
+
 #undef __