[turbofan] delay inserting spill slots for parent ranges.

src/compiler/pipeline.cc

Index: src/compiler/pipeline.cc
diff --git a/src/compiler/pipeline.cc b/src/compiler/pipeline.cc
index c8ce77e00f5df4c6ada56254a687b4a4b6d31f3b..538b0d880aa256251245b5e04847e1daac2e8596 100644
--- a/src/compiler/pipeline.cc
+++ b/src/compiler/pipeline.cc
@@ -559,6 +559,15 @@ struct ReuseSpillSlotsPhase {
 };
 
 
+struct CommitAssignmentPhase {
+  static const char* phase_name() { return "commit assignment"; }
+
+  void Run(PipelineData* data, Zone* temp_zone) {
+    data->register_allocator()->CommitAssignment();
+  }
+};
+
+
 struct PopulatePointerMapsPhase {
   static const char* phase_name() { return "populate pointer maps"; }
 
@@ -990,7 +999,9 @@ void Pipeline::AllocateRegisters(const RegisterConfiguration* config,
     os << "----- Instruction sequence before register allocation -----\n"
        << printable;
   }
-  DCHECK(!data->register_allocator()->ExistsUseWithoutDefinition());
+  if (verifier != nullptr) {
+    CHECK(!data->register_allocator()->ExistsUseWithoutDefinition());
+  }
   Run<AllocateGeneralRegistersPhase>();
   if (!data->register_allocator()->AllocationOk()) {
     data->set_compilation_failed();
@@ -1004,6 +1015,7 @@ void Pipeline::AllocateRegisters(const RegisterConfiguration* config,
   if (FLAG_turbo_reuse_spill_slots) {
     Run<ReuseSpillSlotsPhase>();
   }
+  Run<CommitAssignmentPhase>();
   Run<PopulatePointerMapsPhase>();
   Run<ConnectRangesPhase>();
   Run<ResolveControlFlowPhase>();