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Issue 785443002: Fix gc on MIPS (live registers were spilled in reversed order). (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_MIPS.
6 #if defined(TARGET_ARCH_MIPS) 6 #if defined(TARGET_ARCH_MIPS)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "vm/ast_printer.h" 10 #include "vm/ast_printer.h"
(...skipping 1472 matching lines...) Expand 10 before | Expand all | Expand 10 after
1483 for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) { 1483 for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
1484 DRegister fpu_reg = static_cast<DRegister>(reg_idx); 1484 DRegister fpu_reg = static_cast<DRegister>(reg_idx);
1485 if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) { 1485 if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
1486 __ StoreDToOffset(fpu_reg, SP, offset); 1486 __ StoreDToOffset(fpu_reg, SP, offset);
1487 offset += kFpuRegisterSize; 1487 offset += kFpuRegisterSize;
1488 } 1488 }
1489 } 1489 }
1490 ASSERT(offset == (fpu_regs_count * kFpuRegisterSize)); 1490 ASSERT(offset == (fpu_regs_count * kFpuRegisterSize));
1491 } 1491 }
1492 1492
1493 // Store general purpose registers with the lowest register number at the 1493 // Store general purpose registers with the highest register number at the
1494 // lowest address. 1494 // lowest address. The order in which the registers are pushed must match the
1495 // order in which the registers are encoded in the safe point's stack map.
1495 const intptr_t cpu_registers = locs->live_registers()->cpu_registers(); 1496 const intptr_t cpu_registers = locs->live_registers()->cpu_registers();
1496 ASSERT((cpu_registers & ~kAllCpuRegistersList) == 0); 1497 ASSERT((cpu_registers & ~kAllCpuRegistersList) == 0);
1497 const int register_count = Utils::CountOneBits(cpu_registers); 1498 const int register_count = Utils::CountOneBits(cpu_registers);
1498 int registers_pushed = 0; 1499 if (register_count > 0) {
1499 1500 __ addiu(SP, SP, Immediate(-register_count * kWordSize));
1500 __ addiu(SP, SP, Immediate(-register_count * kWordSize)); 1501 intptr_t offset = register_count * kWordSize;
1501 for (int i = 0; i < kNumberOfCpuRegisters; i++) { 1502 for (int i = 0; i < kNumberOfCpuRegisters; i++) {
1502 Register r = static_cast<Register>(i); 1503 Register r = static_cast<Register>(i);
1503 if (locs->live_registers()->ContainsRegister(r)) { 1504 if (locs->live_registers()->ContainsRegister(r)) {
1504 __ sw(r, Address(SP, registers_pushed * kWordSize)); 1505 offset -= kWordSize;
1505 registers_pushed++; 1506 __ sw(r, Address(SP, offset));
1507 }
1506 } 1508 }
koda 2014/12/05 00:46:43 ASSERT(offset == 0)?
regis 2014/12/05 00:56:11 Done.
1507 } 1509 }
1508 } 1510 }
1509 1511
1510 1512
1511 void FlowGraphCompiler::RestoreLiveRegisters(LocationSummary* locs) { 1513 void FlowGraphCompiler::RestoreLiveRegisters(LocationSummary* locs) {
1512 // General purpose registers have the lowest register number at the 1514 // General purpose registers have the highest register number at the
1513 // lowest address. 1515 // lowest address.
1514 __ TraceSimMsg("RestoreLiveRegisters"); 1516 __ TraceSimMsg("RestoreLiveRegisters");
1515 const intptr_t cpu_registers = locs->live_registers()->cpu_registers(); 1517 const intptr_t cpu_registers = locs->live_registers()->cpu_registers();
1516 ASSERT((cpu_registers & ~kAllCpuRegistersList) == 0); 1518 ASSERT((cpu_registers & ~kAllCpuRegistersList) == 0);
1517 const int register_count = Utils::CountOneBits(cpu_registers); 1519 const int register_count = Utils::CountOneBits(cpu_registers);
1518 int registers_popped = 0; 1520 if (register_count > 0) {
1519 1521 intptr_t offset = register_count * kWordSize;
1520 for (int i = 0; i < kNumberOfCpuRegisters; i++) { 1522 for (int i = 0; i < kNumberOfCpuRegisters; i++) {
1521 Register r = static_cast<Register>(i); 1523 Register r = static_cast<Register>(i);
1522 if (locs->live_registers()->ContainsRegister(r)) { 1524 if (locs->live_registers()->ContainsRegister(r)) {
1523 __ lw(r, Address(SP, registers_popped * kWordSize)); 1525 offset -= kWordSize;
1524 registers_popped++; 1526 __ lw(r, Address(SP, offset));
1527 }
1525 } 1528 }
1529 __ addiu(SP, SP, Immediate(register_count * kWordSize));
koda 2014/12/05 00:46:43 ASSERT(offset == 0)?
regis 2014/12/05 00:56:11 Done.
1526 } 1530 }
1527 __ addiu(SP, SP, Immediate(register_count * kWordSize));
1528 1531
1529 const intptr_t fpu_regs_count = locs->live_registers()->FpuRegisterCount(); 1532 const intptr_t fpu_regs_count = locs->live_registers()->FpuRegisterCount();
1530 if (fpu_regs_count > 0) { 1533 if (fpu_regs_count > 0) {
1531 // Fpu registers have the lowest register number at the lowest address. 1534 // Fpu registers have the lowest register number at the lowest address.
1532 intptr_t offset = 0; 1535 intptr_t offset = 0;
1533 for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) { 1536 for (intptr_t reg_idx = 0; reg_idx < kNumberOfFpuRegisters; ++reg_idx) {
1534 DRegister fpu_reg = static_cast<DRegister>(reg_idx); 1537 DRegister fpu_reg = static_cast<DRegister>(reg_idx);
1535 if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) { 1538 if (locs->live_registers()->ContainsFpuRegister(fpu_reg)) {
1536 __ LoadDFromOffset(fpu_reg, SP, offset); 1539 __ LoadDFromOffset(fpu_reg, SP, offset);
1537 offset += kFpuRegisterSize; 1540 offset += kFpuRegisterSize;
(...skipping 294 matching lines...) Expand 10 before | Expand all | Expand 10 after
1832 __ AddImmediate(SP, kDoubleSize); 1835 __ AddImmediate(SP, kDoubleSize);
1833 } 1836 }
1834 1837
1835 1838
1836 #undef __ 1839 #undef __
1837 1840
1838 1841
1839 } // namespace dart 1842 } // namespace dart
1840 1843
1841 #endif // defined TARGET_ARCH_MIPS 1844 #endif // defined TARGET_ARCH_MIPS
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