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| 1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
| 6 #include "src/compiler/code-generator-impl.h" | 6 #include "src/compiler/code-generator-impl.h" |
| 7 #include "src/compiler/gap-resolver.h" | 7 #include "src/compiler/gap-resolver.h" |
| 8 #include "src/compiler/node-matchers.h" | 8 #include "src/compiler/node-matchers.h" |
| 9 #include "src/compiler/node-properties-inl.h" | 9 #include "src/compiler/node-properties-inl.h" |
| 10 #include "src/mips/macro-assembler-mips.h" | 10 #include "src/mips/macro-assembler-mips.h" |
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| 159 | 159 |
| 160 void Generate() FINAL { __ mov(result_, zero_reg); } | 160 void Generate() FINAL { __ mov(result_, zero_reg); } |
| 161 | 161 |
| 162 private: | 162 private: |
| 163 Register const result_; | 163 Register const result_; |
| 164 }; | 164 }; |
| 165 | 165 |
| 166 } // namespace | 166 } // namespace |
| 167 | 167 |
| 168 | 168 |
| 169 #define ASSEMBLE_CHECKED_LOAD_FLOAT(width, asm_instr) \ | 169 #define ASSEMBLE_CHECKED_LOAD_FLOAT(width, asm_instr) \ |
| 170 do { \ | 170 do { \ |
| 171 auto result = i.Output##width##Register(); \ | 171 auto result = i.Output##width##Register(); \ |
| 172 auto offset = i.InputRegister(0); \ | 172 auto ool = new (zone()) OutOfLineLoad##width(this, result); \ |
| 173 auto ool = new (zone()) OutOfLineLoad##width(this, result); \ | 173 if (instr->InputAt(0)->IsRegister()) { \ |
| 174 __ Branch(ool->entry(), hs, offset, Operand(i.InputRegister(1))); \ | 174 auto offset = i.InputRegister(0); \ |
| 175 __ Daddu(at, i.InputRegister(2), offset); \ | 175 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ |
| 176 __ asm_instr(result, MemOperand(at, 0)); \ | 176 __ Daddu(at, i.InputRegister(2), offset); \ |
| 177 __ bind(ool->exit()); \ | 177 __ asm_instr(result, MemOperand(at, 0)); \ |
| 178 } else { \ |
| 179 auto offset = i.InputOperand(0).immediate(); \ |
| 180 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \ |
| 181 __ asm_instr(result, MemOperand(i.InputRegister(2), offset)); \ |
| 182 } \ |
| 183 __ bind(ool->exit()); \ |
| 178 } while (0) | 184 } while (0) |
| 179 | 185 |
| 180 | 186 |
| 181 #define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \ | 187 #define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr) \ |
| 182 do { \ | 188 do { \ |
| 183 auto result = i.OutputRegister(); \ | 189 auto result = i.OutputRegister(); \ |
| 184 auto offset = i.InputRegister(0); \ | 190 auto ool = new (zone()) OutOfLineLoadInteger(this, result); \ |
| 185 auto ool = new (zone()) OutOfLineLoadInteger(this, result); \ | 191 if (instr->InputAt(0)->IsRegister()) { \ |
| 186 __ Branch(ool->entry(), hs, offset, Operand(i.InputRegister(1))); \ | 192 auto offset = i.InputRegister(0); \ |
| 187 __ Daddu(at, i.InputRegister(2), offset); \ | 193 __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \ |
| 188 __ asm_instr(result, MemOperand(at, 0)); \ | 194 __ Daddu(at, i.InputRegister(2), offset); \ |
| 189 __ bind(ool->exit()); \ | 195 __ asm_instr(result, MemOperand(at, 0)); \ |
| 196 } else { \ |
| 197 auto offset = i.InputOperand(0).immediate(); \ |
| 198 __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset)); \ |
| 199 __ asm_instr(result, MemOperand(i.InputRegister(2), offset)); \ |
| 200 } \ |
| 201 __ bind(ool->exit()); \ |
| 190 } while (0) | 202 } while (0) |
| 191 | 203 |
| 192 | 204 |
| 193 #define ASSEMBLE_CHECKED_STORE_FLOAT(width, asm_instr) \ | 205 #define ASSEMBLE_CHECKED_STORE_FLOAT(width, asm_instr) \ |
| 194 do { \ | 206 do { \ |
| 195 auto offset = i.InputRegister(0); \ | 207 Label done; \ |
| 196 Label done; \ | 208 if (instr->InputAt(0)->IsRegister()) { \ |
| 197 __ Branch(&done, hs, offset, Operand(i.InputRegister(1))); \ | 209 auto offset = i.InputRegister(0); \ |
| 198 auto value = i.Input##width##Register(2); \ | 210 auto value = i.Input##width##Register(2); \ |
| 199 __ Daddu(at, i.InputRegister(3), offset); \ | 211 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ |
| 200 __ asm_instr(value, MemOperand(at, 0)); \ | 212 __ Daddu(at, i.InputRegister(3), offset); \ |
| 201 __ bind(&done); \ | 213 __ asm_instr(value, MemOperand(at, 0)); \ |
| 214 } else { \ |
| 215 auto offset = i.InputOperand(0).immediate(); \ |
| 216 auto value = i.Input##width##Register(2); \ |
| 217 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \ |
| 218 __ asm_instr(value, MemOperand(i.InputRegister(3), offset)); \ |
| 219 } \ |
| 220 __ bind(&done); \ |
| 202 } while (0) | 221 } while (0) |
| 203 | 222 |
| 204 | 223 |
| 205 #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \ | 224 #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \ |
| 206 do { \ | 225 do { \ |
| 207 auto offset = i.InputRegister(0); \ | 226 Label done; \ |
| 208 Label done; \ | 227 if (instr->InputAt(0)->IsRegister()) { \ |
| 209 __ Branch(&done, hs, offset, Operand(i.InputRegister(1))); \ | 228 auto offset = i.InputRegister(0); \ |
| 210 auto value = i.InputRegister(2); \ | 229 auto value = i.InputRegister(2); \ |
| 211 __ Daddu(at, i.InputRegister(3), offset); \ | 230 __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \ |
| 212 __ asm_instr(value, MemOperand(at, 0)); \ | 231 __ Daddu(at, i.InputRegister(3), offset); \ |
| 213 __ bind(&done); \ | 232 __ asm_instr(value, MemOperand(at, 0)); \ |
| 233 } else { \ |
| 234 auto offset = i.InputOperand(0).immediate(); \ |
| 235 auto value = i.InputRegister(2); \ |
| 236 __ Branch(&done, ls, i.InputRegister(1), Operand(offset)); \ |
| 237 __ asm_instr(value, MemOperand(i.InputRegister(3), offset)); \ |
| 238 } \ |
| 239 __ bind(&done); \ |
| 214 } while (0) | 240 } while (0) |
| 215 | 241 |
| 216 | 242 |
| 217 // Assembles an instruction after register allocation, producing machine code. | 243 // Assembles an instruction after register allocation, producing machine code. |
| 218 void CodeGenerator::AssembleArchInstruction(Instruction* instr) { | 244 void CodeGenerator::AssembleArchInstruction(Instruction* instr) { |
| 219 MipsOperandConverter i(this, instr); | 245 MipsOperandConverter i(this, instr); |
| 220 InstructionCode opcode = instr->opcode(); | 246 InstructionCode opcode = instr->opcode(); |
| 221 | 247 |
| 222 switch (ArchOpcodeField::decode(opcode)) { | 248 switch (ArchOpcodeField::decode(opcode)) { |
| 223 case kArchCallCodeObject: { | 249 case kArchCallCodeObject: { |
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| 1352 } | 1378 } |
| 1353 } | 1379 } |
| 1354 MarkLazyDeoptSite(); | 1380 MarkLazyDeoptSite(); |
| 1355 } | 1381 } |
| 1356 | 1382 |
| 1357 #undef __ | 1383 #undef __ |
| 1358 | 1384 |
| 1359 } // namespace compiler | 1385 } // namespace compiler |
| 1360 } // namespace internal | 1386 } // namespace internal |
| 1361 } // namespace v8 | 1387 } // namespace v8 |
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