MIPS; Improve checked load/store operators for constant offset and length.

src/compiler/mips/instruction-selector-mips.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 24 matching lines @@
     int32_t value = m.Value();
     switch (ArchOpcodeField::decode(opcode)) {
       case kMipsShl:
       case kMipsSar:
       case kMipsShr:
         return is_uint5(value);
       case kMipsXor:
         return is_uint16(value);
       case kMipsLdc1:
       case kMipsSdc1:
+      case kCheckedLoadFloat32:
+      case kCheckedLoadFloat64:
+      case kCheckedStoreFloat32:
+      case kCheckedStoreFloat64:
         return is_int16(value + kIntSize);
       default:
         return is_int16(value);
     }
   }
 
  private:
   bool ImmediateFitsAddrMode1Instruction(int32_t imm) const {
     TRACE_UNIMPL();
     return false;
@@ skipping 451 matching lines @@
     case kRepFloat32:
       opcode = kCheckedLoadFloat32;
       break;
     case kRepFloat64:
       opcode = kCheckedLoadFloat64;
       break;
     default:
       UNREACHABLE();
       return;
   }
-  InstructionOperand* offset_operand = g.UseRegister(offset);
+  InstructionOperand* offset_operand = g.CanBeImmediate(offset, opcode)
+                                           ? g.UseImmediate(offset)
+                                           : g.UseRegister(offset);
+
+  InstructionOperand* length_operand =
+      (!g.CanBeImmediate(offset, opcode)) ? g.CanBeImmediate(length, opcode)
+      ? g.UseImmediate(length)
+      : g.UseRegister(length)
+      : g.UseRegister(length);
+
   Emit(opcode | AddressingModeField::encode(kMode_MRI),
-       g.DefineAsRegister(node), offset_operand, g.UseRegister(length),
+       g.DefineAsRegister(node), offset_operand, length_operand,
        g.UseRegister(buffer));
 }
 
 
 void InstructionSelector::VisitCheckedStore(Node* node) {
   MachineType rep = RepresentationOf(OpParameter<MachineType>(node));
   MipsOperandGenerator g(this);
   Node* const buffer = node->InputAt(0);
   Node* const offset = node->InputAt(1);
   Node* const length = node->InputAt(2);
@@ skipping 12 matching lines @@
     case kRepFloat32:
       opcode = kCheckedStoreFloat32;
       break;
     case kRepFloat64:
       opcode = kCheckedStoreFloat64;
       break;
     default:
       UNREACHABLE();
       return;
   }
-  InstructionOperand* offset_operand = g.UseRegister(offset);
+  InstructionOperand* offset_operand = g.CanBeImmediate(offset, opcode)
+                                           ? g.UseImmediate(offset)
+                                           : g.UseRegister(offset);
+
+  InstructionOperand* length_operand =
+      (!g.CanBeImmediate(offset, opcode)) ? g.CanBeImmediate(length, opcode)
+      ? g.UseImmediate(length)
+      : g.UseRegister(length)
+      : g.UseRegister(length);
+
   Emit(opcode | AddressingModeField::encode(kMode_MRI), nullptr, offset_operand,
-       g.UseRegister(length), g.UseRegister(value), g.UseRegister(buffer));
+       length_operand, g.UseRegister(value), g.UseRegister(buffer));
 }
 
 
 namespace {
 
 // Shared routine for multiple compare operations.
 static void VisitCompare(InstructionSelector* selector, InstructionCode opcode,
                          InstructionOperand* left, InstructionOperand* right,
                          FlagsContinuation* cont) {
   MipsOperandGenerator g(selector);
@@ skipping 219 matching lines @@
 
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   return MachineOperatorBuilder::kNoFlags;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8