Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(1068)

Issues Search
    My Issues | Starred     Open | Closed | All

Unified Diff: src/trusted/validator_arm/armv7-thumb.table

Issue 7799013: Intial Thumb2 Sandbox (naclrev 6680) Base URL: svn://svn.chromium.org/native_client/trunk/src/native_client
Patch Set: fix comma Created 9 years, 3 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« src/trusted/validator_arm/address_set.h ('K') | « src/trusted/validator_arm/address_set.cc ('k') | src/trusted/validator_arm/build.scons » ('j') | src/trusted/validator_arm/build.scons » ('J')
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: src/trusted/validator_arm/armv7-thumb.table
diff --git a/src/trusted/validator_arm/armv7-thumb.table b/src/trusted/validator_arm/armv7-thumb.table
new file mode 100644
index 0000000000000000000000000000000000000000..e48f2ba328f059336dd3d0cbb3f50c1d28cb6005
--- /dev/null
+++ b/src/trusted/validator_arm/armv7-thumb.table
@@ -0,0 +1,421 @@
+# ARMv7 Instruction Encodings
+#
+# This table is derived from the "ARM Architecture Reference Manual, ARMv7-A
+# and ARMv7-R edition" and is used here with the permission of ARM Limited.
+# Reproduction for purposes other than the development and distribution of
+# Native Client may require the explicit permission of ARM Limited.
+
+# This file defines the Native Client "instruction classes" assigned to every
+# possible ARMv7 instruction encoding. It is organized into a series of tables,
+# and directly parallels the ARM Architecture Reference Manual cited above.
+#
+# Each table consists of
+# - A name,
+# - A citation in the Architecture Reference Manual,
+# - One or more columns defining bitfields to match, and
+# - One or more rows describing patterns in those bitfields.
+#
+# A leading tilde (~) negates a pattern. A hyphen (-) is short for a string of
+# don't-care bits (x). A double-quote (") indicates that a pattern is the same
+# as the row above it.
+#
+# Each row may specify a terminal instruction class ("=InstClass"), or forward
+# the reader to a different table ("->table_name").
+#
+# If an encoding is not valid in every ARM architecture rev, the instruction
+# class may indicate the rev or feature that makes the encoding valid in
+# parentheses.
+#
+# This table is for the decoding of Thumb mode instructions.
+
+-- ARMv7_Thumb (See Section A6.1)
+bittage(15:11)
+11101 ->thumb32 #(v6T2)
+11110 "
+11111 "
+- ->thumb16
+
+-- thumb16 (See Section A6.2)
+opcode(15:10)
+00xxxx ->dp_shifted_imm
+010000 ->dp
+010001 ->special_and_bx
+01001x =LDRLitT1(v4T) # LDR (literal) T1 A8-122
+0101xx ->ldst_single
+011xxx "
+100xxx "
+10100x =ADRT1(v4T) # ADR T1 A8-32
+10101x =SPMod(v4T) # ADD (SP plus immediate) T1 A8-28
+1011xx ->misc16
+11000x =STMT1(v4T) # STM* T1 A8-374
+11001x =LDMT1(v4T) # LDM* T1 A8-110
+1101xx ->cond_br_and_svc
+11100x =BranchT2(v4T) # B T2 A8-44
+
+-- dp_shifted_imm (See Section A6.2.1)
+opcode(13:9)
+000xx =Def3 # LSL (immediate) T1 A8-178
+001xx =Def3 # LSR (immediate) T1 A8-182
+010xx =Def3 # ASR (immediate) T1 A8-40
+01100 =Def3 # ADD (register) T1 A8-24
+01101 =Def3 # SUB (register) T1 A8-422
+01110 =Def3 # ADD (immediate, 3-bit) T1 A8-20
+01111 =Def3 # SUB (immediate, 3-bit) T1 A8-418
+100xx =Def8_10 # MOV (immediate) T1 A8-194
+101xx =Cmp # CMP (immediate) T1 A8-80
+110xx =Def8_10 # ADD (immediate, 8-bit) T2 A8-20
+111xx =Def8_10 # SUB (immediate, 8-bit) T2 A8-418
+
+-- dp (See Section A6.2.2)
+opcode(9:6)
+0000 =Mask3 # AND (register) T1 A8-36
+0001 =Def3 # EOR (register) T1 A8-96
+0010 =Def3 # LSL (register) T1 A8-180
+0011 =Def3 # LSR (register) T1 A8-184
+0100 =Def3 # ASR (register) T1 A8-42
+0101 =Def3 # ADC (register) T1 A8-16
+0110 =Def3 # SBC (register) T1 A8-304
+0111 =Def3 # ROR (register) T1 A8-280
+1000 =Cmp # TST (register) T1 A8-456
+1001 =Def3 # RSB (immediate) T1 A8-284
+1010 =Cmp # CMP (high register) T1 A8-82
+1011 =Cmp # CMN (register) T1 A8-76
+1100 =OrMask3 # ORR (register) T1 A8-230
+1101 =Def3 # MUL T1 A8-212
+1110 =BiC3 # BIC (register) T1 A8-52
+1111 =Def3 # MVN T1 A8-216
+
+-- special_and_bx (See Section A6.2.3)
+opcode(9:6) safety(2:0)
+0000 - =Def3(v6T2) # ADD (low register) T2 A8-24
+0001 - =Def3(v4T) # ADD (high register) T2 A8-24
+001x - "
+0100 - =Unpredictable
+0101 - =Cmp(v4T) # CMP (high register) T2 A8-82
+011x - "
+1000 - =MovT(v6) # MOV (low register) T1 A8-196
+1001 - =MovT(v4T) # MOV (high register) T1 A8-196
+101x - "
+110x - =BXT(v4T) # BX T1 A8-62
+111x 000 =BLXT(v5T) # BLX (register) T1 A8-60
+
+-- ldst_single (See Section A6.2.4)
+opA(15:12) opB(11:9)
+0101 000 =MemOpThumbStore # STR (register)
+" 001 " # STRH (register)
+" 010 " # STRB (register)
+" 011 =MemOpThumbLoad # LDRSB (register)
+" 100 " # LDR (register)
+" 101 " # LDRH (register)
+" 110 " # LDRB (register)
+" 111 " # LDRSH (register)
+0110 0xx =MemOpThumbStore # STR (immediate)
+0111 " " # STRB (immediate)
+1000 " " # STRH (immediate)
+0110 1xx =MemOpThumbLoad # LDR (immediate)
+0111 " " # LDRB (immediate)
+1000 " " # LDRH (immediate)
+1001 0xx =MemOpSPThumbStore # STR (immediate, SP Relative)
+1001 1xx =MemOpSPThumbLoad # LDR (immediate, SP Relative)
+
+-- misc16 (See Section A6.2.5)
+opcode(11:5)
+0110010 =Forbidden(v6) # SETEND
+0110011 =Forbidden(v6) # CPS
+00000xx =SPMod(v4T) # ADD (SP plus immediate)
+00001xx =SPMod(v4T) # SUB (SP minus immediate)
+0001xxx =CmpBrZ(v6T2) # CBNZ, CBZ
+0011xxx "
+1001xxx "
+1011xxx "
+001000x =Def3(v6) # SXTH
+001001x " # SXTB
+001010x " # UXTH
+001011x " # UXTB
+101000x " # REV
+101001x " # REV16
+101011x " # REVSH
+010xxxx =PushMult(v4T) # PUSH
+110xxxx =PopMult(v4T) # POP
+1110xxx =ThumbBreakpoint(v5) # BPKT
+1111xxx ->it_and_hints
+
+-- it_and_hints (See Section A6.2.5 subsection)
+opA(7:4) opB(3:0)
+- ~0000 =IT(v6T2) # IT
+0000 0000 =EffectiveNoOp(v6T2) # NOP
+0001 0000 =Forbidden(v7) # YIELD
+0010 0000 " # WFE
+0011 0000 " # WFI
+0100 0000 " # SEV
+
+-- cond_br_and_svc (See Section A6.2.6)
+opcode(11:8)
+~111x =BranchT2 # B
+1110 =Undefined
+1111 =Forbidden # SVC/SWI
+
+-- thumb32 (See Section A6.3)
+op1(12:11) op2(10:4) op(31)
+01 00xx0xx - ->ldstm # (v6T2)
+" 00xx1xx - ->ldstduex_and_tbr
+" 01xxxxx - ->dp_shifted_reg
+" 1xxxxxx - ->coprocessor
+10 x0xxxxx 0 ->dp_mod_imm
+" x1xxxxx 0 ->dp_imm
+" - 1 ->br_misc
+11 000xxx0 - ->st_single
+" 001xxx0 - ->asimd
+" 00xx001 - ->ldb_and_hint
+" 00xx011 - ->ldh_and_hint
+" 00xx101 - ->ldw
+" 00xx111 - =Undefined
+" 010xxxx - ->dp_reg
+" 0110xxx - ->math
+" 0111xxx - ->math2
+" 1xxxxxx - ->coprocessor2
+
+-- dp_mod_imm (See Section A6.3.1)
+op(8:5) Rn(3:0) Rd(27:24) S(4:4)
+0000 - ~1111 x =DPMImm # AND (immediate)
+" - 1111 0 =Unpredictable
+" - 1111 1 =Cmp # TST (immediate)
+0001 - - - =BicModImmT # BIC (immediate)
+0010 ~1111 - - =OrrModImmT # ORR (immediate)
+" 1111 - - =DPMImm # MOV (immediate)
+0011 ~1111 - - =DPMImm # ORN (immediate)
+" 1111 - - =DPMImm # MVN (immediate)
+0100 - ~1111 x =DPMImm # EOR (immediate)
+" - 1111 0 =Unpredictable
+" - " 1 =Cmp # TEQ (immediate)
+1000 - ~1111 x =DPMImm # ADD (immediate)
+" - 1111 0 =Unpredictable
+" - " 1 =Cmp # CMN (immediate)
+1010 - - - =DPMImm # ADC (immediate)
+1011 - - - =DPMImm # SBC (immediate)
+1101 - ~1111 - =DPMImm # SUB (immediate)
+" - 1111 0 =Unpredictable
+" - " 1 =Cmp # CMP (immediate)
+1110 - - - =DPMImm # RSB (immediate)
+
+-- dp_imm (See Section A6.3.3)
+op(8:4) Rn(3:0) safety(30:22)
+00000 ~1111 - =DPMImm # ADD (immediate)
+" 1111 - =DPMImm # ADR (immediate)
+00100 - - =DPMImm # MOV (immediate)
+01010 ~1111 - =DPMImm # SUB (immediate)
+" 1111 - =DPMImm # ADR (immediate)
+01100 - - =DPMImm # MOVT (immediate)
+100x0 - ~000xxxx00 =DPMImm # SSAT (immediate)
+10010 - 000xxxx00 =DPMImm # SSAT16 (immediate)
+10100 - - =DPMImm # SBFX (immediate)
+10110 ~1111 - =DPMImm # BFI
+" 1111 - =DPMImm # BFC
+110x0 - ~000xxxx00 =DPMImm # USAT
+11010 - 000xxxx00 =DPMImm # USAT16
+11100 - - =DPMImm # UBFX
+
+-- br_misc (See Section A6.3.4-1)
+op1(30:28) op(10:4) op2(27:24)
+0x0 ~x111xxx - =BranchT3(v6T2) # B
+" 0111000 xx00 =Forbidden # MSR (App)
+" " xx01 =Forbidden # MSR (Sys)
+" " xx1x "
+" 0111001 - "
+" 0111010 - ->cps_and_hints
+" 0111011 - ->misc_ctl
+" 0111100 - =Forbidden(v6T2) # BXJ
+" 0111101 - =Unimplemented(v6T2) # SUBS PC, LR, #const
+" 011111x - =Forbidden(v6T2) # MRS
+000 1111111 - =Forbidden # SMC/SMI
+010 1111111 - =Undefined
+0x1 - - =BranchT4(v6T2) # B
+1x0 - - =Forbidden(v5T) # BLX
+1x1 - - =BLT # BL
+
+-- cps_and_hints (See Section A6.3.4-2)
+op1(26:24) op2(23:16)
+~000 - =Forbidden(v6T2) # CPS
+000 00000000 =EffectiveNoOp(v6T2) # NOP
+" 00000001 =Forbidden # YIELD
+" 00000010 " # WFE
+" 00000011 " # WFI
+" 00000100 " # SEV
+" 1111xxxx " # DBG
+
+-- misc_ctl (See Section A6.3.4-3)
+op(23:20)
+0000 =Forbidden # ENTERX
+0001 =Forbidden # LEAVEX
+0010 =EffectiveNoOp(v7) # CLREX
+0011 " # DSB
+0101 " # DMB
+0110 " # ISB
+
+-- ldstm (See Section A6.3.5)
+op(8:7) L(4:4) Rn(3:0)
+00 0 - =Forbidden # SRS
+" 1 - =Forbidden # RFE
+01 0 - =STMTD # STM/IA/EA
+" 1 ~1101 =LDMTD # LDM/IA/EA
+" " 1101 =LDMTD # POP
+10 0 ~1101 =STMTD # STMDB/FD
+" " 1101 =STMTD # PUSH
+" 1 - =LDMTD # LDMDB/FD
+11 0 - =Forbidden # SRS
+" 1 - =Forbidden # RFE
+
+-- ldstduex_and_tbr (See A6.3.6)
+op1(8:7) op2(5:4) op3(23:20) Rn(3:0)
+00 00 - - =StrEx # STREX
+" 01 - - =LdrEx # LDREX
+0x 10 - - =StrS # STRD
+1x x0 " " "
+0x 11 - ~1111 =LdrD # LDRD
+1x x1 - " "
+0x 11 - 1111 =Forbidden
+# I am banning this because it appears to cause a decode loop in the spec
+# On actual CPUs, this seems to cause an Illegal Instruction exception.
+1x 01 - 1111 =LdrD # LDRD literal (e.g. constpool)
+# Note, I have forced a bit here to prevent us from leaving spec land. The spec
+# is not self consistent. A8.6.67 contradicts this line in the table, and I'm
+# trusting it, as it was a marked up change
+01 00 0100 - =StrEx # STREXB
+" " 0101 - " # STREXH
+" " 0111 - =StrExD # STREXD
+" 01 0000 - =Forbidden # TBB # Bundle size needs to be
+" " 0001 - " # TBH # at least 18 to implement
+ # or we need masking logic
+" " 0100 - =LdrEx # LDREXB
+" " 0101 - " # LDREXH
+" " 0111 - =LdrExD # LDREXD
+
+-- ldw (A6.3.7)
+op1(8:7) op2(27:22) Rn(3:0)
+01 - ~1111 =LDRImmT3 # LDR
+00 1xx1xx " =LDRImmT4
+" 1100xx " "
+" 1110xx " " # LDRT
+" 000000 " " # LDR
+0x - 1111 =Def31_18 # LDR
+
+-- ldh_and_hint (A6.3.8)
+op1(8:7) op2(27:22) Rn(3:0) Rt(31:28)
+0x - 1111 ~1111 =LDRImmT3 # LDRH
+01 - ~1111 1111 "
+00 1xx1xx ~1111 ~1111 =LDRImmT4
+" 1100xx " " =LDRImmT3
+" 1110xx " " " # LDRHT
+" 000000 " " " # LDRH
+1x - 1111 ~1111 " # LDRSH
+11 - ~1111 1111 "
+10 1xx1xx ~1111 ~1111 =LDRImmT4
+" 1100xx " " =LDRImmT3
+" 1110xx " " " # LDRSHT
+" 000000 " " " # LDRSH
+0x - 1111 1111 =Unpredictable
+01 - ~1111 1111 =EffectiveNoOp # PLD/PLDW
+00 1100xx ~1111 1111 "
+" 000000 ~1111 1111 "
+00 1xx1xx ~1111 1111 =Unpredictable
+" 1110xx ~1111 1111 "
+1x - 1111 1111 =EffectiveNoOp # Unallocated hint
+10 1100xx ~1111 1111 "
+" 000000 ~1111 1111 "
+" 1xx1xx " " =Unpredictable
+" 1110xx " " "
+11 - " " =EffectiveNoOp # Unallocated hint
+
+-- ldb_and_hint (A.6.3.9)
+op1(8:7) op2(27:22) Rn(3:0) Rt(31:28)
+0x - 1111 ~1111 =LDRImmT3 # LDRB
+01 - ~1111 1111 "
+00 1xx1xx ~1111 ~1111 =LDRImmT4
+" 1100xx " " =LDRImmT3
+" 1110xx " " " # LDRBT
+" 000000 " " " # LDRB
+1x - 1111 ~1111 " # LDRSB
+11 - ~1111 1111 "
+10 1xx1xx ~1111 ~1111 =LDRImmT4
+" 1100xx " " =LDRImmT3
+" 1110xx " " " # LDRSBT
+" 000000 " " " # LDRSB
+0x - 1111 1111 =EffectiveNoOp # PLD
+01 - ~1111 1111 =EffectiveNoOp # PLD/PLDW
+00 1100xx ~1111 1111 "
+" 000000 ~1111 1111 "
+00 1xx1xx ~1111 1111 =Unpredictable
+" 1110xx ~1111 1111 "
+1x - 1111 1111 =EffectiveNoOp # PLI
+11 - " " "
+10 1100xx ~1111 1111 "
+" 000000 ~1111 1111 "
+" 1xx1xx " " =Unpredictable
+" 1110xx " " "
+
+-- st_single (A6.3.10)
+op1(7:5) op2(27:22)
+100 - =StrS # STRB
+000 1xx1xx "
+" 1100xx "
+" 1110xx " # STRBT
+" 0xxxxx " # STRB
+101 - " # STRH
+001 1xx1xx "
+" 1100xx "
+" 1110xx " # STRHT
+" 0xxxxx " # STRH
+110 - " # STR
+010 1xx1xx "
+" 1100xx "
+" 1110xx " # STRT
+" 0xxxxx " # STR
+
+-- dp_shifted_reg (A6.3.11)
+op(8:5) Rn(3:0) Rd(27:24) S(4:4)
+0000 - ~1111 x =Def27_24 # AND
+" " 1111 0 =Unpredictable
+" " " 1 =Cmp # TST
+0001 - - - =Def27_24 # BIC
+0010 ~1111 - - =Def27_24 # ORR
+" 1111 - - =Def27_24 # MOV
+0011 ~1111 - - =Def27_24 # ORN
+" 1111 - - =Def27_24 # MVN
+0100 ~1111 - - =Def27_24 # EOR
+" 1111 - 0 =Unpredictable
+" " - 1 =Cmp # TEQ
+0110 - - - =Def27_24 # PKH
+1000 ~1111 - - =Def27_24 # ADD
+" 1111 - 0 =Unpredictable
+" " - 1 =Cmp # CMN
+1010 - - - =Def27_24 # ADC
+1011 - - - =Def27_24 # SBC
+1101 ~1111 - - =Def27_24 # SUB
+" 1111 - 0 =Unpredictable
+" " - 1 =Cmp # CMP
+1011 - - - =Def27_24 # RSB
+
+
+-- coprocessor ( )
+op(0:0)
+- =Unimplemented
+
+-- asimd ( )
+op(0:0)
+- =Unimplemented
+
+-- dp_reg ( )
+op(0:0)
+- =Unimplemented
+
+-- math ( )
+op(0:0)
+- =Unimplemented
+
+-- math2 ( )
+op(0:0)
+- =Unimplemented
+
+-- coprocessor2 ( )
+op(0:0)
+- =Unimplemented
« src/trusted/validator_arm/address_set.h ('K') | « src/trusted/validator_arm/address_set.cc ('k') | src/trusted/validator_arm/build.scons » ('j') | src/trusted/validator_arm/build.scons » ('J')

Powered by Google App Engine
This is Rietveld 408576698