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| 1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. | 
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be | 
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. | 
| 4 | 4 | 
| 5 #include <limits.h>  // For LONG_MIN, LONG_MAX. | 5 #include <limits.h>  // For LONG_MIN, LONG_MAX. | 
| 6 | 6 | 
| 7 #include "src/v8.h" | 7 #include "src/v8.h" | 
| 8 | 8 | 
| 9 #if V8_TARGET_ARCH_MIPS64 | 9 #if V8_TARGET_ARCH_MIPS64 | 
| 10 | 10 | 
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| 1710       } | 1710       } | 
| 1711     } | 1711     } | 
| 1712   } | 1712   } | 
| 1713 | 1713 | 
| 1714   if (bd == PROTECT) { | 1714   if (bd == PROTECT) { | 
| 1715     nop(); | 1715     nop(); | 
| 1716   } | 1716   } | 
| 1717 } | 1717 } | 
| 1718 | 1718 | 
| 1719 | 1719 | 
|  | 1720 void MacroAssembler::Move(FPURegister dst, float imm) { | 
|  | 1721   li(at, Operand(bit_cast<int32_t>(imm))); | 
|  | 1722   mtc1(at, dst); | 
|  | 1723 } | 
|  | 1724 | 
|  | 1725 | 
| 1720 void MacroAssembler::Move(FPURegister dst, double imm) { | 1726 void MacroAssembler::Move(FPURegister dst, double imm) { | 
| 1721   static const DoubleRepresentation minus_zero(-0.0); | 1727   static const DoubleRepresentation minus_zero(-0.0); | 
| 1722   static const DoubleRepresentation zero(0.0); | 1728   static const DoubleRepresentation zero(0.0); | 
| 1723   DoubleRepresentation value_rep(imm); | 1729   DoubleRepresentation value_rep(imm); | 
| 1724   // Handle special values first. | 1730   // Handle special values first. | 
| 1725   if (value_rep == zero && has_double_zero_reg_set_) { | 1731   if (value_rep == zero && has_double_zero_reg_set_) { | 
| 1726     mov_d(dst, kDoubleRegZero); | 1732     mov_d(dst, kDoubleRegZero); | 
| 1727   } else if (value_rep == minus_zero && has_double_zero_reg_set_) { | 1733   } else if (value_rep == minus_zero && has_double_zero_reg_set_) { | 
| 1728     neg_d(dst, kDoubleRegZero); | 1734     neg_d(dst, kDoubleRegZero); | 
| 1729   } else { | 1735   } else { | 
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| 6325   } | 6331   } | 
| 6326   if (mag.shift > 0) sra(result, result, mag.shift); | 6332   if (mag.shift > 0) sra(result, result, mag.shift); | 
| 6327   srl(at, dividend, 31); | 6333   srl(at, dividend, 31); | 
| 6328   Addu(result, result, Operand(at)); | 6334   Addu(result, result, Operand(at)); | 
| 6329 } | 6335 } | 
| 6330 | 6336 | 
| 6331 | 6337 | 
| 6332 } }  // namespace v8::internal | 6338 } }  // namespace v8::internal | 
| 6333 | 6339 | 
| 6334 #endif  // V8_TARGET_ARCH_MIPS64 | 6340 #endif  // V8_TARGET_ARCH_MIPS64 | 
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