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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1042 } | 1042 } |
1043 void pextrd(const Operand& dst, XMMRegister src, int8_t offset); | 1043 void pextrd(const Operand& dst, XMMRegister src, int8_t offset); |
1044 void pinsrd(XMMRegister dst, Register src, int8_t offset) { | 1044 void pinsrd(XMMRegister dst, Register src, int8_t offset) { |
1045 pinsrd(dst, Operand(src), offset); | 1045 pinsrd(dst, Operand(src), offset); |
1046 } | 1046 } |
1047 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset); | 1047 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset); |
1048 | 1048 |
1049 // Parallel XMM operations. | 1049 // Parallel XMM operations. |
1050 void movntdqa(XMMRegister dst, const Operand& src); | 1050 void movntdqa(XMMRegister dst, const Operand& src); |
1051 void movntdq(const Operand& dst, XMMRegister src); | 1051 void movntdq(const Operand& dst, XMMRegister src); |
| 1052 |
| 1053 // AVX instructions |
| 1054 void vaddsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { |
| 1055 vaddsd(dst, src1, Operand(src2)); |
| 1056 } |
| 1057 void vaddsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { |
| 1058 vsd(0x58, dst, src1, src2); |
| 1059 } |
| 1060 void vsubsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { |
| 1061 vsubsd(dst, src1, Operand(src2)); |
| 1062 } |
| 1063 void vsubsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { |
| 1064 vsd(0x5c, dst, src1, src2); |
| 1065 } |
| 1066 void vmulsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { |
| 1067 vmulsd(dst, src1, Operand(src2)); |
| 1068 } |
| 1069 void vmulsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { |
| 1070 vsd(0x59, dst, src1, src2); |
| 1071 } |
| 1072 void vdivsd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { |
| 1073 vdivsd(dst, src1, Operand(src2)); |
| 1074 } |
| 1075 void vdivsd(XMMRegister dst, XMMRegister src1, const Operand& src2) { |
| 1076 vsd(0x5e, dst, src1, src2); |
| 1077 } |
| 1078 void vsd(byte op, XMMRegister dst, XMMRegister src1, const Operand& src2); |
| 1079 |
1052 // Prefetch src position into cache level. | 1080 // Prefetch src position into cache level. |
1053 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a | 1081 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a |
1054 // non-temporal | 1082 // non-temporal |
1055 void prefetch(const Operand& src, int level); | 1083 void prefetch(const Operand& src, int level); |
1056 // TODO(lrn): Need SFENCE for movnt? | 1084 // TODO(lrn): Need SFENCE for movnt? |
1057 | 1085 |
1058 // Check the code size generated from label to here. | 1086 // Check the code size generated from label to here. |
1059 int SizeOfCodeGeneratedSince(Label* label) { | 1087 int SizeOfCodeGeneratedSince(Label* label) { |
1060 return pc_offset() - label->pos(); | 1088 return pc_offset() - label->pos(); |
1061 } | 1089 } |
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1145 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81) | 1173 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81) |
1146 // with a given destination expression and an immediate operand. It attempts | 1174 // with a given destination expression and an immediate operand. It attempts |
1147 // to use the shortest encoding possible. | 1175 // to use the shortest encoding possible. |
1148 // sel specifies the /n in the modrm byte (see the Intel PRM). | 1176 // sel specifies the /n in the modrm byte (see the Intel PRM). |
1149 void emit_arith(int sel, Operand dst, const Immediate& x); | 1177 void emit_arith(int sel, Operand dst, const Immediate& x); |
1150 | 1178 |
1151 void emit_operand(Register reg, const Operand& adr); | 1179 void emit_operand(Register reg, const Operand& adr); |
1152 | 1180 |
1153 void emit_farith(int b1, int b2, int i); | 1181 void emit_farith(int b1, int b2, int i); |
1154 | 1182 |
| 1183 // Emit vex prefix |
| 1184 enum SIMDPrefix { kNone = 0x0, k66 = 0x1, kF3 = 0x2, kF2 = 0x3 }; |
| 1185 enum VectorLength { kL128 = 0x0, kL256 = 0x4, kLIG = kL128 }; |
| 1186 enum VexW { kW0 = 0x0, kW1 = 0x80, kWIG = kW0 }; |
| 1187 enum LeadingOpcode { k0F = 0x1, k0F38 = 0x2, k0F3A = 0x2 }; |
| 1188 inline void emit_vex_prefix(XMMRegister v, VectorLength l, SIMDPrefix pp, |
| 1189 LeadingOpcode m, VexW w); |
| 1190 |
1155 // labels | 1191 // labels |
1156 void print(Label* L); | 1192 void print(Label* L); |
1157 void bind_to(Label* L, int pos); | 1193 void bind_to(Label* L, int pos); |
1158 | 1194 |
1159 // displacements | 1195 // displacements |
1160 inline Displacement disp_at(Label* L); | 1196 inline Displacement disp_at(Label* L); |
1161 inline void disp_at_put(Label* L, Displacement disp); | 1197 inline void disp_at_put(Label* L, Displacement disp); |
1162 inline void emit_disp(Label* L, Displacement::Type type); | 1198 inline void emit_disp(Label* L, Displacement::Type type); |
1163 inline void emit_near_disp(Label* L); | 1199 inline void emit_near_disp(Label* L); |
1164 | 1200 |
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1199 private: | 1235 private: |
1200 Assembler* assembler_; | 1236 Assembler* assembler_; |
1201 #ifdef DEBUG | 1237 #ifdef DEBUG |
1202 int space_before_; | 1238 int space_before_; |
1203 #endif | 1239 #endif |
1204 }; | 1240 }; |
1205 | 1241 |
1206 } } // namespace v8::internal | 1242 } } // namespace v8::internal |
1207 | 1243 |
1208 #endif // V8_IA32_ASSEMBLER_IA32_H_ | 1244 #endif // V8_IA32_ASSEMBLER_IA32_H_ |
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