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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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52 V(MipsLh) \ | 52 V(MipsLh) \ |
53 V(MipsLhu) \ | 53 V(MipsLhu) \ |
54 V(MipsSh) \ | 54 V(MipsSh) \ |
55 V(MipsLw) \ | 55 V(MipsLw) \ |
56 V(MipsSw) \ | 56 V(MipsSw) \ |
57 V(MipsLwc1) \ | 57 V(MipsLwc1) \ |
58 V(MipsSwc1) \ | 58 V(MipsSwc1) \ |
59 V(MipsLdc1) \ | 59 V(MipsLdc1) \ |
60 V(MipsSdc1) \ | 60 V(MipsSdc1) \ |
61 V(MipsPush) \ | 61 V(MipsPush) \ |
| 62 V(MipsStoreToStackSlot) \ |
| 63 V(MipsStackClaim) \ |
62 V(MipsStoreWriteBarrier) | 64 V(MipsStoreWriteBarrier) |
63 | 65 |
64 | 66 |
65 // Addressing modes represent the "shape" of inputs to an instruction. | 67 // Addressing modes represent the "shape" of inputs to an instruction. |
66 // Many instructions support multiple addressing modes. Addressing modes | 68 // Many instructions support multiple addressing modes. Addressing modes |
67 // are encoded into the InstructionCode of the instruction and tell the | 69 // are encoded into the InstructionCode of the instruction and tell the |
68 // code generator after register allocation which assembler method to call. | 70 // code generator after register allocation which assembler method to call. |
69 // | 71 // |
70 // We use the following local notation for addressing modes: | 72 // We use the following local notation for addressing modes: |
71 // | 73 // |
72 // R = register | 74 // R = register |
73 // O = register or stack slot | 75 // O = register or stack slot |
74 // D = double register | 76 // D = double register |
75 // I = immediate (handle, external, int32) | 77 // I = immediate (handle, external, int32) |
76 // MRI = [register + immediate] | 78 // MRI = [register + immediate] |
77 // MRR = [register + register] | 79 // MRR = [register + register] |
78 // TODO(plind): Add the new r6 address modes. | 80 // TODO(plind): Add the new r6 address modes. |
79 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 81 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
80 V(MRI) /* [%r0 + K] */ \ | 82 V(MRI) /* [%r0 + K] */ \ |
81 V(MRR) /* [%r0 + %r1] */ | 83 V(MRR) /* [%r0 + %r1] */ |
82 | 84 |
83 | 85 |
84 } // namespace compiler | 86 } // namespace compiler |
85 } // namespace internal | 87 } // namespace internal |
86 } // namespace v8 | 88 } // namespace v8 |
87 | 89 |
88 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 90 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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