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Side by Side Diff: runtime/vm/flow_graph_compiler_arm64.cc

Issue 760383005: Fix parallel move code for swapping SIMD registers on ARM and ARM64. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM64.
6 #if defined(TARGET_ARCH_ARM64) 6 #if defined(TARGET_ARCH_ARM64)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "vm/ast_printer.h" 10 #include "vm/ast_printer.h"
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1664 destination.base_reg(), destination.ToStackSlotOffset()); 1664 destination.base_reg(), destination.ToStackSlotOffset());
1665 } else if (source.IsStackSlot() && destination.IsRegister()) { 1665 } else if (source.IsStackSlot() && destination.IsRegister()) {
1666 Exchange(destination.reg(), 1666 Exchange(destination.reg(),
1667 source.base_reg(), source.ToStackSlotOffset()); 1667 source.base_reg(), source.ToStackSlotOffset());
1668 } else if (source.IsStackSlot() && destination.IsStackSlot()) { 1668 } else if (source.IsStackSlot() && destination.IsStackSlot()) {
1669 Exchange(source.base_reg(), source.ToStackSlotOffset(), 1669 Exchange(source.base_reg(), source.ToStackSlotOffset(),
1670 destination.base_reg(), destination.ToStackSlotOffset()); 1670 destination.base_reg(), destination.ToStackSlotOffset());
1671 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { 1671 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
1672 const VRegister dst = destination.fpu_reg(); 1672 const VRegister dst = destination.fpu_reg();
1673 const VRegister src = source.fpu_reg(); 1673 const VRegister src = source.fpu_reg();
1674 __ fmovdd(VTMP, src); 1674 __ vmov(VTMP, src);
1675 __ fmovdd(src, dst); 1675 __ vmov(src, dst);
1676 __ fmovdd(dst, VTMP); 1676 __ vmov(dst, VTMP);
1677 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { 1677 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
1678 ASSERT(destination.IsDoubleStackSlot() || 1678 ASSERT(destination.IsDoubleStackSlot() ||
1679 destination.IsQuadStackSlot() || 1679 destination.IsQuadStackSlot() ||
1680 source.IsDoubleStackSlot() || 1680 source.IsDoubleStackSlot() ||
1681 source.IsQuadStackSlot()); 1681 source.IsQuadStackSlot());
1682 bool double_width = destination.IsDoubleStackSlot() || 1682 bool double_width = destination.IsDoubleStackSlot() ||
1683 source.IsDoubleStackSlot(); 1683 source.IsDoubleStackSlot();
1684 VRegister reg = source.IsFpuRegister() ? source.fpu_reg() 1684 VRegister reg = source.IsFpuRegister() ? source.fpu_reg()
1685 : destination.fpu_reg(); 1685 : destination.fpu_reg();
1686 Register base_reg = source.IsFpuRegister() 1686 Register base_reg = source.IsFpuRegister()
1687 ? destination.base_reg() 1687 ? destination.base_reg()
1688 : source.base_reg(); 1688 : source.base_reg();
1689 const intptr_t slot_offset = source.IsFpuRegister() 1689 const intptr_t slot_offset = source.IsFpuRegister()
1690 ? destination.ToStackSlotOffset() 1690 ? destination.ToStackSlotOffset()
1691 : source.ToStackSlotOffset(); 1691 : source.ToStackSlotOffset();
1692 1692
1693 if (double_width) { 1693 if (double_width) {
1694 __ LoadDFromOffset(VTMP, base_reg, slot_offset, PP); 1694 __ LoadDFromOffset(VTMP, base_reg, slot_offset, PP);
1695 __ StoreDToOffset(reg, base_reg, slot_offset, PP); 1695 __ StoreDToOffset(reg, base_reg, slot_offset, PP);
1696 __ fmovdd(reg, VTMP); 1696 __ fmovdd(reg, VTMP);
1697 } else { 1697 } else {
1698 __ LoadQFromOffset(VTMP, base_reg, slot_offset, PP); 1698 __ LoadQFromOffset(VTMP, base_reg, slot_offset, PP);
1699 __ StoreQToOffset(reg, base_reg, slot_offset, PP); 1699 __ StoreQToOffset(reg, base_reg, slot_offset, PP);
1700 __ fmovdd(reg, VTMP); 1700 __ vmov(reg, VTMP);
1701 } 1701 }
1702 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { 1702 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
1703 const intptr_t source_offset = source.ToStackSlotOffset(); 1703 const intptr_t source_offset = source.ToStackSlotOffset();
1704 const intptr_t dest_offset = destination.ToStackSlotOffset(); 1704 const intptr_t dest_offset = destination.ToStackSlotOffset();
1705 1705
1706 ScratchFpuRegisterScope ensure_scratch(this, kNoFpuRegister); 1706 ScratchFpuRegisterScope ensure_scratch(this, kNoFpuRegister);
1707 VRegister scratch = ensure_scratch.reg(); 1707 VRegister scratch = ensure_scratch.reg();
1708 __ LoadDFromOffset(VTMP, source.base_reg(), source_offset, PP); 1708 __ LoadDFromOffset(VTMP, source.base_reg(), source_offset, PP);
1709 __ LoadDFromOffset(scratch, destination.base_reg(), dest_offset, PP); 1709 __ LoadDFromOffset(scratch, destination.base_reg(), dest_offset, PP);
1710 __ StoreDToOffset(VTMP, destination.base_reg(), dest_offset, PP); 1710 __ StoreDToOffset(VTMP, destination.base_reg(), dest_offset, PP);
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1807 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) { 1807 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) {
1808 __ PopDouble(reg); 1808 __ PopDouble(reg);
1809 } 1809 }
1810 1810
1811 1811
1812 #undef __ 1812 #undef __
1813 1813
1814 } // namespace dart 1814 } // namespace dart
1815 1815
1816 #endif // defined TARGET_ARCH_ARM64 1816 #endif // defined TARGET_ARCH_ARM64
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