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1 ; This test checks that undef values are represented as zero. | 1 ; This test checks that undef values are represented as zero. |
2 | 2 |
3 ; RUN: %p2i -i %s --args -O2 --verbose none \ | 3 ; RUN: %p2i -i %s --args -O2 --verbose none \ |
4 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ | 4 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ |
5 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | 5 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s |
6 ; RUN: %p2i -i %s --args -Om1 --verbose none \ | 6 ; RUN: %p2i -i %s --args -Om1 --verbose none \ |
7 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ | 7 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ |
8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s | 8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s |
9 ; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \ | 9 ; RUN: %p2i -i %s --args -O2 -mattr=sse4.1 --verbose none \ |
10 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ | 10 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ |
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26 ; CHECK-LABEL: undef_i64 | 26 ; CHECK-LABEL: undef_i64 |
27 ; CHECK-DAG: mov eax, 0 | 27 ; CHECK-DAG: mov eax, 0 |
28 ; CHECK-DAG: mov edx, 0 | 28 ; CHECK-DAG: mov edx, 0 |
29 ; CHECK: ret | 29 ; CHECK: ret |
30 } | 30 } |
31 | 31 |
32 define float @undef_float() { | 32 define float @undef_float() { |
33 entry: | 33 entry: |
34 ret float undef | 34 ret float undef |
35 ; CHECK-LABEL: undef_float | 35 ; CHECK-LABEL: undef_float |
36 ; CHECK: fld dword ptr [4] | 36 ; CHECK: fld dword ptr [.L$float$0] |
37 } | 37 } |
38 | 38 |
39 define <4 x i1> @undef_v4i1() { | 39 define <4 x i1> @undef_v4i1() { |
40 entry: | 40 entry: |
41 ret <4 x i1> undef | 41 ret <4 x i1> undef |
42 ; CHECK-LABEL: undef_v4i1 | 42 ; CHECK-LABEL: undef_v4i1 |
43 ; CHECK: pxor | 43 ; CHECK: pxor |
44 } | 44 } |
45 | 45 |
46 define <8 x i1> @undef_v8i1() { | 46 define <8 x i1> @undef_v8i1() { |
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179 ret <4 x float> %val | 179 ret <4 x float> %val |
180 ; CHECK-LABEL: vector_insertelement_arg1 | 180 ; CHECK-LABEL: vector_insertelement_arg1 |
181 ; CHECK: pxor | 181 ; CHECK: pxor |
182 } | 182 } |
183 | 183 |
184 define <4 x float> @vector_insertelement_arg2(<4 x float> %arg) { | 184 define <4 x float> @vector_insertelement_arg2(<4 x float> %arg) { |
185 entry: | 185 entry: |
186 %val = insertelement <4 x float> %arg, float undef, i32 0 | 186 %val = insertelement <4 x float> %arg, float undef, i32 0 |
187 ret <4 x float> %val | 187 ret <4 x float> %val |
188 ; CHECK-LABEL: vector_insertelement_arg2 | 188 ; CHECK-LABEL: vector_insertelement_arg2 |
189 ; CHECK: movss {{.*}}, dword ptr [4] | 189 ; CHECK: movss {{.*}}, dword ptr [.L$float$0] |
190 } | 190 } |
191 | 191 |
192 define float @vector_extractelement_v4f32_index_0() { | 192 define float @vector_extractelement_v4f32_index_0() { |
193 entry: | 193 entry: |
194 %val = extractelement <4 x float> undef, i32 0 | 194 %val = extractelement <4 x float> undef, i32 0 |
195 ret float %val | 195 ret float %val |
196 ; CHECK-LABEL: vector_extractelement_v4f32_index_0 | 196 ; CHECK-LABEL: vector_extractelement_v4f32_index_0 |
197 ; CHECK: pxor | 197 ; CHECK: pxor |
198 } | 198 } |
199 | 199 |
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278 ; CHECK: pxor | 278 ; CHECK: pxor |
279 } | 279 } |
280 | 280 |
281 define <4 x float> @vector_select_v4f32_arg2(<4 x i1> %cond, <4 x float> %a) { | 281 define <4 x float> @vector_select_v4f32_arg2(<4 x i1> %cond, <4 x float> %a) { |
282 entry: | 282 entry: |
283 %val = select <4 x i1> %cond, <4 x float> %a, <4 x float> undef | 283 %val = select <4 x i1> %cond, <4 x float> %a, <4 x float> undef |
284 ret <4 x float> %val | 284 ret <4 x float> %val |
285 ; CHECK-LABEL: vector_select_v4f32_arg2 | 285 ; CHECK-LABEL: vector_select_v4f32_arg2 |
286 ; CHECK: pxor | 286 ; CHECK: pxor |
287 } | 287 } |
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