Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(460)

Side by Side Diff: tests_lit/llvm2ice_tests/convert.ll

Issue 756543002: Subzero: Fix new issues after the LLVM 3.5 merge. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Also use `llvm-config --system-libs` Created 6 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « tests_lit/llvm2ice_tests/64bit.pnacl.ll ('k') | tests_lit/llvm2ice_tests/ebp_args.ll » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 ; Simple test of signed and unsigned integer conversions. 1 ; Simple test of signed and unsigned integer conversions.
2 2
3 ; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we 3 ; TODO(jvoung): llvm-objdump doesn't symbolize global symbols well, so we
4 ; have [0] == i8v, [2] == i16v, [4] == i32v, [8] == i64v, etc. 4 ; have [0] == i8v, [2] == i16v, [4] == i32v, [8] == i64v, etc.
5 5
6 ; RUN: %p2i -i %s --args -O2 --verbose none \ 6 ; RUN: %p2i -i %s --args -O2 --verbose none \
7 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ 7 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s 8 ; RUN: | llvm-objdump -d --symbolize -x86-asm-syntax=intel - | FileCheck %s
9 ; RUN: %p2i -i %s --args -Om1 --verbose none \ 9 ; RUN: %p2i -i %s --args -Om1 --verbose none \
10 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \ 10 ; RUN: | llvm-mc -triple=i686-none-nacl -filetype=obj \
(...skipping 24 matching lines...) Expand all
35 ret void 35 ret void
36 } 36 }
37 ; CHECK-LABEL: from_int8 37 ; CHECK-LABEL: from_int8
38 ; CHECK: mov {{.*}}, byte ptr [ 38 ; CHECK: mov {{.*}}, byte ptr [
39 ; CHECK: movsx e{{.*}}, {{[a-d]l|byte ptr}} 39 ; CHECK: movsx e{{.*}}, {{[a-d]l|byte ptr}}
40 ; CHECK: mov word ptr [ 40 ; CHECK: mov word ptr [
41 ; CHECK: movsx 41 ; CHECK: movsx
42 ; CHECK: mov dword ptr [ 42 ; CHECK: mov dword ptr [
43 ; CHECK: movsx 43 ; CHECK: movsx
44 ; CHECK: sar {{.*}}, 31 44 ; CHECK: sar {{.*}}, 31
45 ; This appears to be a bug in llvm-mc. It should be [8] and [12] to represent 45 ; This appears to be a bug in llvm-mc. It should be i64v and i64+4.
46 ; i64v and i64+4. 46 ; CHECK-DAG: [.bss]
47 ; CHECK-DAG: [8] 47 ; CHECK-DAG: [.bss]
48 ; CHECK-DAG: [8]
49 48
50 define void @from_int16() { 49 define void @from_int16() {
51 entry: 50 entry:
52 %__0 = bitcast [2 x i8]* @i16v to i16* 51 %__0 = bitcast [2 x i8]* @i16v to i16*
53 %v0 = load i16* %__0, align 1 52 %v0 = load i16* %__0, align 1
54 %v1 = trunc i16 %v0 to i8 53 %v1 = trunc i16 %v0 to i8
55 %__3 = bitcast [1 x i8]* @i8v to i8* 54 %__3 = bitcast [1 x i8]* @i8v to i8*
56 store i8 %v1, i8* %__3, align 1 55 store i8 %v1, i8* %__3, align 1
57 %v2 = sext i16 %v0 to i32 56 %v2 = sext i16 %v0 to i32
58 %__5 = bitcast [4 x i8]* @i32v to i32* 57 %__5 = bitcast [4 x i8]* @i32v to i32*
59 store i32 %v2, i32* %__5, align 1 58 store i32 %v2, i32* %__5, align 1
60 %v3 = sext i16 %v0 to i64 59 %v3 = sext i16 %v0 to i64
61 %__7 = bitcast [8 x i8]* @i64v to i64* 60 %__7 = bitcast [8 x i8]* @i64v to i64*
62 store i64 %v3, i64* %__7, align 1 61 store i64 %v3, i64* %__7, align 1
63 ret void 62 ret void
64 } 63 }
65 ; CHECK-LABEL: from_int16 64 ; CHECK-LABEL: from_int16
66 ; CHECK: mov {{.*}}, word ptr [ 65 ; CHECK: mov {{.*}}, word ptr [
67 ; CHECK: [0] 66 ; CHECK: [.bss]
68 ; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}} 67 ; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
69 ; CHECK: [4] 68 ; CHECK: [.bss]
70 ; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}} 69 ; CHECK: movsx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
71 ; CHECK: sar {{.*}}, 31 70 ; CHECK: sar {{.*}}, 31
72 ; CHECK: [8] 71 ; CHECK: [.bss]
73 72
74 define void @from_int32() { 73 define void @from_int32() {
75 entry: 74 entry:
76 %__0 = bitcast [4 x i8]* @i32v to i32* 75 %__0 = bitcast [4 x i8]* @i32v to i32*
77 %v0 = load i32* %__0, align 1 76 %v0 = load i32* %__0, align 1
78 %v1 = trunc i32 %v0 to i8 77 %v1 = trunc i32 %v0 to i8
79 %__3 = bitcast [1 x i8]* @i8v to i8* 78 %__3 = bitcast [1 x i8]* @i8v to i8*
80 store i8 %v1, i8* %__3, align 1 79 store i8 %v1, i8* %__3, align 1
81 %v2 = trunc i32 %v0 to i16 80 %v2 = trunc i32 %v0 to i16
82 %__5 = bitcast [2 x i8]* @i16v to i16* 81 %__5 = bitcast [2 x i8]* @i16v to i16*
83 store i16 %v2, i16* %__5, align 1 82 store i16 %v2, i16* %__5, align 1
84 %v3 = sext i32 %v0 to i64 83 %v3 = sext i32 %v0 to i64
85 %__7 = bitcast [8 x i8]* @i64v to i64* 84 %__7 = bitcast [8 x i8]* @i64v to i64*
86 store i64 %v3, i64* %__7, align 1 85 store i64 %v3, i64* %__7, align 1
87 ret void 86 ret void
88 } 87 }
89 ; CHECK-LABEL: from_int32 88 ; CHECK-LABEL: from_int32
90 ; CHECK: [4] 89 ; CHECK: [.bss]
91 ; CHECK: [0] 90 ; CHECK: [.bss]
92 ; CHECK: [2] 91 ; CHECK: [.bss]
93 ; CHECK: sar {{.*}}, 31 92 ; CHECK: sar {{.*}}, 31
94 ; CHECK: [8] 93 ; CHECK: [.bss]
95 94
96 define void @from_int64() { 95 define void @from_int64() {
97 entry: 96 entry:
98 %__0 = bitcast [8 x i8]* @i64v to i64* 97 %__0 = bitcast [8 x i8]* @i64v to i64*
99 %v0 = load i64* %__0, align 1 98 %v0 = load i64* %__0, align 1
100 %v1 = trunc i64 %v0 to i8 99 %v1 = trunc i64 %v0 to i8
101 %__3 = bitcast [1 x i8]* @i8v to i8* 100 %__3 = bitcast [1 x i8]* @i8v to i8*
102 store i8 %v1, i8* %__3, align 1 101 store i8 %v1, i8* %__3, align 1
103 %v2 = trunc i64 %v0 to i16 102 %v2 = trunc i64 %v0 to i16
104 %__5 = bitcast [2 x i8]* @i16v to i16* 103 %__5 = bitcast [2 x i8]* @i16v to i16*
105 store i16 %v2, i16* %__5, align 1 104 store i16 %v2, i16* %__5, align 1
106 %v3 = trunc i64 %v0 to i32 105 %v3 = trunc i64 %v0 to i32
107 %__7 = bitcast [4 x i8]* @i32v to i32* 106 %__7 = bitcast [4 x i8]* @i32v to i32*
108 store i32 %v3, i32* %__7, align 1 107 store i32 %v3, i32* %__7, align 1
109 ret void 108 ret void
110 } 109 }
111 ; CHECK-LABEL: from_int64 110 ; CHECK-LABEL: from_int64
112 ; CHECK: [8] 111 ; CHECK: [.bss]
113 ; CHECK: [0] 112 ; CHECK: [.bss]
114 ; CHECK: [2] 113 ; CHECK: [.bss]
115 ; CHECK: [4] 114 ; CHECK: [.bss]
116 115
117 116
118 define void @from_uint8() { 117 define void @from_uint8() {
119 entry: 118 entry:
120 %__0 = bitcast [1 x i8]* @u8v to i8* 119 %__0 = bitcast [1 x i8]* @u8v to i8*
121 %v0 = load i8* %__0, align 1 120 %v0 = load i8* %__0, align 1
122 %v1 = zext i8 %v0 to i16 121 %v1 = zext i8 %v0 to i16
123 %__3 = bitcast [2 x i8]* @i16v to i16* 122 %__3 = bitcast [2 x i8]* @i16v to i16*
124 store i16 %v1, i16* %__3, align 1 123 store i16 %v1, i16* %__3, align 1
125 %v2 = zext i8 %v0 to i32 124 %v2 = zext i8 %v0 to i32
126 %__5 = bitcast [4 x i8]* @i32v to i32* 125 %__5 = bitcast [4 x i8]* @i32v to i32*
127 store i32 %v2, i32* %__5, align 1 126 store i32 %v2, i32* %__5, align 1
128 %v3 = zext i8 %v0 to i64 127 %v3 = zext i8 %v0 to i64
129 %__7 = bitcast [8 x i8]* @i64v to i64* 128 %__7 = bitcast [8 x i8]* @i64v to i64*
130 store i64 %v3, i64* %__7, align 1 129 store i64 %v3, i64* %__7, align 1
131 ret void 130 ret void
132 } 131 }
133 ; CHECK-LABEL: from_uint8 132 ; CHECK-LABEL: from_uint8
134 ; CHECK: [16] 133 ; CHECK: [.bss]
135 ; CHECK: movzx e{{.*}}, {{[a-d]l|byte ptr}} 134 ; CHECK: movzx e{{.*}}, {{[a-d]l|byte ptr}}
136 ; CHECK: [2] 135 ; CHECK: [.bss]
137 ; CHECK: movzx 136 ; CHECK: movzx
138 ; CHECK: [4] 137 ; CHECK: [.bss]
139 ; CHECK: movzx 138 ; CHECK: movzx
140 ; CHECK: mov {{.*}}, 0 139 ; CHECK: mov {{.*}}, 0
141 ; CHECK: [8] 140 ; CHECK: [.bss]
142 141
143 define void @from_uint16() { 142 define void @from_uint16() {
144 entry: 143 entry:
145 %__0 = bitcast [2 x i8]* @u16v to i16* 144 %__0 = bitcast [2 x i8]* @u16v to i16*
146 %v0 = load i16* %__0, align 1 145 %v0 = load i16* %__0, align 1
147 %v1 = trunc i16 %v0 to i8 146 %v1 = trunc i16 %v0 to i8
148 %__3 = bitcast [1 x i8]* @i8v to i8* 147 %__3 = bitcast [1 x i8]* @i8v to i8*
149 store i8 %v1, i8* %__3, align 1 148 store i8 %v1, i8* %__3, align 1
150 %v2 = zext i16 %v0 to i32 149 %v2 = zext i16 %v0 to i32
151 %__5 = bitcast [4 x i8]* @i32v to i32* 150 %__5 = bitcast [4 x i8]* @i32v to i32*
152 store i32 %v2, i32* %__5, align 1 151 store i32 %v2, i32* %__5, align 1
153 %v3 = zext i16 %v0 to i64 152 %v3 = zext i16 %v0 to i64
154 %__7 = bitcast [8 x i8]* @i64v to i64* 153 %__7 = bitcast [8 x i8]* @i64v to i64*
155 store i64 %v3, i64* %__7, align 1 154 store i64 %v3, i64* %__7, align 1
156 ret void 155 ret void
157 } 156 }
158 ; CHECK-LABEL: from_uint16 157 ; CHECK-LABEL: from_uint16
159 ; CHECK: [18] 158 ; CHECK: [.bss]
160 ; CHECK: [0] 159 ; CHECK: [.bss]
161 ; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}} 160 ; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
162 ; CHECK: [4] 161 ; CHECK: [.bss]
163 ; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}} 162 ; CHECK: movzx e{{.*}}, {{.*x|[ds]i|bp|word ptr}}
164 ; CHECK: mov {{.*}}, 0 163 ; CHECK: mov {{.*}}, 0
165 ; CHECK: [8] 164 ; CHECK: [.bss]
166 165
167 define void @from_uint32() { 166 define void @from_uint32() {
168 entry: 167 entry:
169 %__0 = bitcast [4 x i8]* @u32v to i32* 168 %__0 = bitcast [4 x i8]* @u32v to i32*
170 %v0 = load i32* %__0, align 1 169 %v0 = load i32* %__0, align 1
171 %v1 = trunc i32 %v0 to i8 170 %v1 = trunc i32 %v0 to i8
172 %__3 = bitcast [1 x i8]* @i8v to i8* 171 %__3 = bitcast [1 x i8]* @i8v to i8*
173 store i8 %v1, i8* %__3, align 1 172 store i8 %v1, i8* %__3, align 1
174 %v2 = trunc i32 %v0 to i16 173 %v2 = trunc i32 %v0 to i16
175 %__5 = bitcast [2 x i8]* @i16v to i16* 174 %__5 = bitcast [2 x i8]* @i16v to i16*
176 store i16 %v2, i16* %__5, align 1 175 store i16 %v2, i16* %__5, align 1
177 %v3 = zext i32 %v0 to i64 176 %v3 = zext i32 %v0 to i64
178 %__7 = bitcast [8 x i8]* @i64v to i64* 177 %__7 = bitcast [8 x i8]* @i64v to i64*
179 store i64 %v3, i64* %__7, align 1 178 store i64 %v3, i64* %__7, align 1
180 ret void 179 ret void
181 } 180 }
182 ; CHECK-LABEL: from_uint32 181 ; CHECK-LABEL: from_uint32
183 ; CHECK: [20] 182 ; CHECK: [.bss]
184 ; CHECK: [0] 183 ; CHECK: [.bss]
185 ; CHECK: [2] 184 ; CHECK: [.bss]
186 ; CHECK: mov {{.*}}, 0 185 ; CHECK: mov {{.*}}, 0
187 ; CHECK: [8] 186 ; CHECK: [.bss]
188 187
189 define void @from_uint64() { 188 define void @from_uint64() {
190 entry: 189 entry:
191 %__0 = bitcast [8 x i8]* @u64v to i64* 190 %__0 = bitcast [8 x i8]* @u64v to i64*
192 %v0 = load i64* %__0, align 1 191 %v0 = load i64* %__0, align 1
193 %v1 = trunc i64 %v0 to i8 192 %v1 = trunc i64 %v0 to i8
194 %__3 = bitcast [1 x i8]* @i8v to i8* 193 %__3 = bitcast [1 x i8]* @i8v to i8*
195 store i8 %v1, i8* %__3, align 1 194 store i8 %v1, i8* %__3, align 1
196 %v2 = trunc i64 %v0 to i16 195 %v2 = trunc i64 %v0 to i16
197 %__5 = bitcast [2 x i8]* @i16v to i16* 196 %__5 = bitcast [2 x i8]* @i16v to i16*
198 store i16 %v2, i16* %__5, align 1 197 store i16 %v2, i16* %__5, align 1
199 %v3 = trunc i64 %v0 to i32 198 %v3 = trunc i64 %v0 to i32
200 %__7 = bitcast [4 x i8]* @i32v to i32* 199 %__7 = bitcast [4 x i8]* @i32v to i32*
201 store i32 %v3, i32* %__7, align 1 200 store i32 %v3, i32* %__7, align 1
202 ret void 201 ret void
203 } 202 }
204 ; CHECK-LABEL: from_uint64 203 ; CHECK-LABEL: from_uint64
205 ; CHECK: [24] 204 ; CHECK: [.bss]
206 ; CHECK: [0] 205 ; CHECK: [.bss]
207 ; CHECK: [2] 206 ; CHECK: [.bss]
208 ; CHECK: [4] 207 ; CHECK: [.bss]
OLDNEW
« no previous file with comments | « tests_lit/llvm2ice_tests/64bit.pnacl.ll ('k') | tests_lit/llvm2ice_tests/ebp_args.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698