| Index: src/compiler/arm/instruction-selector-arm.cc
|
| diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
|
| index 7d3243e614bcc4665d9354ac8c38353630477e7e..6e1e0846da4217fa7ef90aa990fa4d2a75aca47a 100644
|
| --- a/src/compiler/arm/instruction-selector-arm.cc
|
| +++ b/src/compiler/arm/instruction-selector-arm.cc
|
| @@ -854,16 +854,16 @@
|
|
|
| void InstructionSelector::VisitFloat64Add(Node* node) {
|
| ArmOperandGenerator g(this);
|
| - Float64BinopMatcher m(node);
|
| + Int32BinopMatcher m(node);
|
| if (m.left().IsFloat64Mul() && CanCover(node, m.left().node())) {
|
| - Float64BinopMatcher mleft(m.left().node());
|
| + Int32BinopMatcher mleft(m.left().node());
|
| Emit(kArmVmlaF64, g.DefineSameAsFirst(node),
|
| g.UseRegister(m.right().node()), g.UseRegister(mleft.left().node()),
|
| g.UseRegister(mleft.right().node()));
|
| return;
|
| }
|
| if (m.right().IsFloat64Mul() && CanCover(node, m.right().node())) {
|
| - Float64BinopMatcher mright(m.right().node());
|
| + Int32BinopMatcher mright(m.right().node());
|
| Emit(kArmVmlaF64, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
|
| g.UseRegister(mright.left().node()),
|
| g.UseRegister(mright.right().node()));
|
| @@ -875,14 +875,9 @@
|
|
|
| void InstructionSelector::VisitFloat64Sub(Node* node) {
|
| ArmOperandGenerator g(this);
|
| - Float64BinopMatcher m(node);
|
| - if (m.left().IsMinusZero()) {
|
| - Emit(kArmVnegF64, g.DefineAsRegister(node),
|
| - g.UseRegister(m.right().node()));
|
| - return;
|
| - }
|
| + Int32BinopMatcher m(node);
|
| if (m.right().IsFloat64Mul() && CanCover(node, m.right().node())) {
|
| - Float64BinopMatcher mright(m.right().node());
|
| + Int32BinopMatcher mright(m.right().node());
|
| Emit(kArmVmlsF64, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()),
|
| g.UseRegister(mright.left().node()),
|
| g.UseRegister(mright.right().node()));
|
| @@ -893,7 +888,13 @@
|
|
|
|
|
| void InstructionSelector::VisitFloat64Mul(Node* node) {
|
| - VisitRRRFloat64(this, kArmVmulF64, node);
|
| + ArmOperandGenerator g(this);
|
| + Float64BinopMatcher m(node);
|
| + if (m.right().Is(-1.0)) {
|
| + Emit(kArmVnegF64, g.DefineAsRegister(node), g.UseRegister(m.left().node()));
|
| + } else {
|
| + VisitRRRFloat64(this, kArmVmulF64, node);
|
| + }
|
| }
|
|
|
|
|
|
|