[turbofan]: delay ssa deconstruction in register allocator

src/compiler/instruction.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/common-operator.h"
 #include "src/compiler/generic-node-inl.h"
 #include "src/compiler/graph.h"
 #include "src/compiler/instruction.h"
 
 namespace v8 {
@@ skipping 626 matching lines @@
     os << "  instructions: [" << block->code_start() << ", "
        << block->code_end() << ")\n  predecessors:";
 
     for (auto pred : block->predecessors()) {
       const InstructionBlock* pred_block = code.InstructionBlockAt(pred);
       os << " B" << pred_block->id();
     }
     os << "\n";
 
     for (auto phi : block->phis()) {
-      os << "     phi: v" << phi->virtual_register() << " =";
-      for (auto op_vreg : phi->operands()) {
-        os << " v" << op_vreg;
+      PrintableInstructionOperand printable_op = {
+          printable.register_configuration_, phi->output()};
+      os << "     phi: " << printable_op << " =";
+      for (auto input : phi->inputs()) {
+        printable_op.op_ = input;
+        os << " " << printable_op;
       }
       os << "\n";
     }
 
     ScopedVector<char> buf(32);
     PrintableInstruction printable_instr;
     printable_instr.register_configuration_ = printable.register_configuration_;
     for (int j = block->first_instruction_index();
          j <= block->last_instruction_index(); j++) {
       // TODO(svenpanne) Add some basic formatting to our streams.
       SNPrintF(buf, "%5d", j);
       printable_instr.instr_ = code.InstructionAt(j);
       os << "   " << buf.start() << ": " << printable_instr << "\n";
     }
 
     for (auto succ : block->successors()) {
       const InstructionBlock* succ_block = code.InstructionBlockAt(succ);
       os << " B" << succ_block->id();
     }
     os << "\n";
   }
   return os;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8