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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> | 5 #include <limits.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdlib.h> | 7 #include <stdlib.h> |
8 #include <cmath> | 8 #include <cmath> |
9 | 9 |
10 #include "src/v8.h" | 10 #include "src/v8.h" |
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2081 *alu_out = get_register(LO); | 2081 *alu_out = get_register(LO); |
2082 break; | 2082 break; |
2083 case MULT: // MULT == D_MUL_MUH. | 2083 case MULT: // MULT == D_MUL_MUH. |
2084 // TODO(plind) - Unify MULT/DMULT with single set of 64-bit HI/Lo | 2084 // TODO(plind) - Unify MULT/DMULT with single set of 64-bit HI/Lo |
2085 // regs. | 2085 // regs. |
2086 // TODO(plind) - make the 32-bit MULT ops conform to spec regarding | 2086 // TODO(plind) - make the 32-bit MULT ops conform to spec regarding |
2087 // checking of 32-bit input values, and un-define operations of HW. | 2087 // checking of 32-bit input values, and un-define operations of HW. |
2088 *i64hilo = rs * rt; | 2088 *i64hilo = rs * rt; |
2089 break; | 2089 break; |
2090 case MULTU: | 2090 case MULTU: |
2091 *u64hilo = static_cast<uint64_t>(rs_u) * static_cast<uint64_t>(rt_u); | 2091 *u64hilo = static_cast<uint64_t>(rs_u & 0xffffffff) * |
| 2092 static_cast<uint64_t>(rt_u & 0xffffffff); |
2092 break; | 2093 break; |
2093 case DMULT: // DMULT == D_MUL_MUH. | 2094 case DMULT: // DMULT == D_MUL_MUH. |
2094 if (kArchVariant != kMips64r6) { | 2095 if (kArchVariant != kMips64r6) { |
2095 *i128resultH = MultiplyHighSigned(rs, rt); | 2096 *i128resultH = MultiplyHighSigned(rs, rt); |
2096 *i128resultL = rs * rt; | 2097 *i128resultL = rs * rt; |
2097 } else { | 2098 } else { |
2098 switch (instr->SaValue()) { | 2099 switch (instr->SaValue()) { |
2099 case MUL_OP: | 2100 case MUL_OP: |
2100 *i128resultL = rs * rt; | 2101 *i128resultL = rs * rt; |
2101 break; | 2102 break; |
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2223 } | 2224 } |
2224 break; | 2225 break; |
2225 case SPECIAL3: | 2226 case SPECIAL3: |
2226 switch (instr->FunctionFieldRaw()) { | 2227 switch (instr->FunctionFieldRaw()) { |
2227 case INS: { // Mips32r2 instruction. | 2228 case INS: { // Mips32r2 instruction. |
2228 // Interpret rd field as 5-bit msb of insert. | 2229 // Interpret rd field as 5-bit msb of insert. |
2229 uint16_t msb = rd_reg; | 2230 uint16_t msb = rd_reg; |
2230 // Interpret sa field as 5-bit lsb of insert. | 2231 // Interpret sa field as 5-bit lsb of insert. |
2231 uint16_t lsb = sa; | 2232 uint16_t lsb = sa; |
2232 uint16_t size = msb - lsb + 1; | 2233 uint16_t size = msb - lsb + 1; |
2233 uint32_t mask = (1 << size) - 1; | 2234 uint64_t mask = (1ULL << size) - 1; |
2234 *alu_out = (rt_u & ~(mask << lsb)) | ((rs_u & mask) << lsb); | 2235 *alu_out = (rt_u & ~(mask << lsb)) | ((rs_u & mask) << lsb); |
2235 break; | 2236 break; |
2236 } | 2237 } |
2237 case EXT: { // Mips32r2 instruction. | 2238 case EXT: { // Mips32r2 instruction. |
2238 // Interpret rd field as 5-bit msb of extract. | 2239 // Interpret rd field as 5-bit msb of extract. |
2239 uint16_t msb = rd_reg; | 2240 uint16_t msb = rd_reg; |
2240 // Interpret sa field as 5-bit lsb of extract. | 2241 // Interpret sa field as 5-bit lsb of extract. |
2241 uint16_t lsb = sa; | 2242 uint16_t lsb = sa; |
2242 uint16_t size = msb + 1; | 2243 uint16_t size = msb + 1; |
2243 uint32_t mask = (1 << size) - 1; | 2244 uint64_t mask = (1ULL << size) - 1; |
2244 *alu_out = (rs_u & (mask << lsb)) >> lsb; | 2245 *alu_out = static_cast<int32_t>((rs_u & (mask << lsb)) >> lsb); |
| 2246 break; |
| 2247 } |
| 2248 case DEXT: { // Mips32r2 instruction. |
| 2249 // Interpret rd field as 5-bit msb of extract. |
| 2250 uint16_t msb = rd_reg; |
| 2251 // Interpret sa field as 5-bit lsb of extract. |
| 2252 uint16_t lsb = sa; |
| 2253 uint16_t size = msb + 1; |
| 2254 uint64_t mask = (1ULL << size) - 1; |
| 2255 *alu_out = static_cast<int64_t>((rs_u & (mask << lsb)) >> lsb); |
2245 break; | 2256 break; |
2246 } | 2257 } |
2247 default: | 2258 default: |
2248 UNREACHABLE(); | 2259 UNREACHABLE(); |
2249 } | 2260 } |
2250 break; | 2261 break; |
2251 default: | 2262 default: |
2252 UNREACHABLE(); | 2263 UNREACHABLE(); |
2253 } | 2264 } |
2254 } | 2265 } |
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2776 } | 2787 } |
2777 break; | 2788 break; |
2778 case SPECIAL3: | 2789 case SPECIAL3: |
2779 switch (instr->FunctionFieldRaw()) { | 2790 switch (instr->FunctionFieldRaw()) { |
2780 case INS: | 2791 case INS: |
2781 // Ins instr leaves result in Rt, rather than Rd. | 2792 // Ins instr leaves result in Rt, rather than Rd. |
2782 set_register(rt_reg, alu_out); | 2793 set_register(rt_reg, alu_out); |
2783 TraceRegWr(alu_out); | 2794 TraceRegWr(alu_out); |
2784 break; | 2795 break; |
2785 case EXT: | 2796 case EXT: |
2786 // Ext instr leaves result in Rt, rather than Rd. | 2797 case DEXT: |
| 2798 // Dext/Ext instr leaves result in Rt, rather than Rd. |
2787 set_register(rt_reg, alu_out); | 2799 set_register(rt_reg, alu_out); |
2788 TraceRegWr(alu_out); | 2800 TraceRegWr(alu_out); |
2789 break; | 2801 break; |
2790 default: | 2802 default: |
2791 UNREACHABLE(); | 2803 UNREACHABLE(); |
2792 } | 2804 } |
2793 break; | 2805 break; |
2794 // Unimplemented opcodes raised an error in the configuration step before, | 2806 // Unimplemented opcodes raised an error in the configuration step before, |
2795 // so we can use the default here to set the destination register in common | 2807 // so we can use the default here to set the destination register in common |
2796 // cases. | 2808 // cases. |
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2808 int64_t rs = get_register(instr->RsValue()); | 2820 int64_t rs = get_register(instr->RsValue()); |
2809 uint64_t rs_u = static_cast<uint64_t>(rs); | 2821 uint64_t rs_u = static_cast<uint64_t>(rs); |
2810 int64_t rt_reg = instr->RtValue(); // Destination register. | 2822 int64_t rt_reg = instr->RtValue(); // Destination register. |
2811 int64_t rt = get_register(rt_reg); | 2823 int64_t rt = get_register(rt_reg); |
2812 int16_t imm16 = instr->Imm16Value(); | 2824 int16_t imm16 = instr->Imm16Value(); |
2813 | 2825 |
2814 int32_t ft_reg = instr->FtValue(); // Destination register. | 2826 int32_t ft_reg = instr->FtValue(); // Destination register. |
2815 int64_t ft = get_fpu_register(ft_reg); | 2827 int64_t ft = get_fpu_register(ft_reg); |
2816 | 2828 |
2817 // Zero extended immediate. | 2829 // Zero extended immediate. |
2818 uint32_t oe_imm16 = 0xffff & imm16; | 2830 uint64_t oe_imm16 = 0xffff & imm16; |
2819 // Sign extended immediate. | 2831 // Sign extended immediate. |
2820 int32_t se_imm16 = imm16; | 2832 int64_t se_imm16 = imm16; |
2821 | 2833 |
2822 // Get current pc. | 2834 // Get current pc. |
2823 int64_t current_pc = get_pc(); | 2835 int64_t current_pc = get_pc(); |
2824 // Next pc. | 2836 // Next pc. |
2825 int64_t next_pc = bad_ra; | 2837 int64_t next_pc = bad_ra; |
2826 | 2838 |
2827 // Used for conditional branch instructions. | 2839 // Used for conditional branch instructions. |
2828 bool do_branch = false; | 2840 bool do_branch = false; |
2829 bool execute_branch_delay_instruction = false; | 2841 bool execute_branch_delay_instruction = false; |
2830 | 2842 |
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3436 } | 3448 } |
3437 | 3449 |
3438 | 3450 |
3439 #undef UNSUPPORTED | 3451 #undef UNSUPPORTED |
3440 | 3452 |
3441 } } // namespace v8::internal | 3453 } } // namespace v8::internal |
3442 | 3454 |
3443 #endif // USE_SIMULATOR | 3455 #endif // USE_SIMULATOR |
3444 | 3456 |
3445 #endif // V8_TARGET_ARCH_MIPS64 | 3457 #endif // V8_TARGET_ARCH_MIPS64 |
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