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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2185 | 2185 |
2186 | 2186 |
2187 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { | 2187 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { |
2188 // Should be called via MacroAssembler::Ext. | 2188 // Should be called via MacroAssembler::Ext. |
2189 // Ext instr has 'rt' field as dest, and two uint5: msb, lsb. | 2189 // Ext instr has 'rt' field as dest, and two uint5: msb, lsb. |
2190 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6); | 2190 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6); |
2191 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); | 2191 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); |
2192 } | 2192 } |
2193 | 2193 |
2194 | 2194 |
| 2195 void Assembler::dext_(Register rt, Register rs, uint16_t pos, uint16_t size) { |
| 2196 // Should be called via MacroAssembler::Ext. |
| 2197 // Dext instr has 'rt' field as dest, and two uint5: msb, lsb. |
| 2198 DCHECK(kArchVariant == kMips64r2 || kArchVariant == kMips64r6); |
| 2199 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, DEXT); |
| 2200 } |
| 2201 |
| 2202 |
2195 void Assembler::pref(int32_t hint, const MemOperand& rs) { | 2203 void Assembler::pref(int32_t hint, const MemOperand& rs) { |
2196 DCHECK(is_uint5(hint) && is_uint16(rs.offset_)); | 2204 DCHECK(is_uint5(hint) && is_uint16(rs.offset_)); |
2197 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) | 2205 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) |
2198 | (rs.offset_); | 2206 | (rs.offset_); |
2199 emit(instr); | 2207 emit(instr); |
2200 } | 2208 } |
2201 | 2209 |
2202 | 2210 |
2203 // --------Coprocessor-instructions---------------- | 2211 // --------Coprocessor-instructions---------------- |
2204 | 2212 |
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2924 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { | 2932 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { |
2925 // No out-of-line constant pool support. | 2933 // No out-of-line constant pool support. |
2926 DCHECK(!FLAG_enable_ool_constant_pool); | 2934 DCHECK(!FLAG_enable_ool_constant_pool); |
2927 return; | 2935 return; |
2928 } | 2936 } |
2929 | 2937 |
2930 | 2938 |
2931 } } // namespace v8::internal | 2939 } } // namespace v8::internal |
2932 | 2940 |
2933 #endif // V8_TARGET_ARCH_MIPS64 | 2941 #endif // V8_TARGET_ARCH_MIPS64 |
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