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| 1 // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. |
| 4 |
| 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
| 7 |
| 8 namespace v8 { |
| 9 namespace internal { |
| 10 namespace compiler { |
| 11 |
| 12 // MIPS64-specific opcodes that specify which assembly sequence to emit. |
| 13 // Most opcodes specify a single instruction. |
| 14 #define TARGET_ARCH_OPCODE_LIST(V) \ |
| 15 V(Mips64Add) \ |
| 16 V(Mips64Dadd) \ |
| 17 V(Mips64Sub) \ |
| 18 V(Mips64Dsub) \ |
| 19 V(Mips64Mul) \ |
| 20 V(Mips64MulHigh) \ |
| 21 V(Mips64MulHighU) \ |
| 22 V(Mips64Dmul) \ |
| 23 V(Mips64Div) \ |
| 24 V(Mips64Ddiv) \ |
| 25 V(Mips64DivU) \ |
| 26 V(Mips64DdivU) \ |
| 27 V(Mips64Mod) \ |
| 28 V(Mips64Dmod) \ |
| 29 V(Mips64ModU) \ |
| 30 V(Mips64DmodU) \ |
| 31 V(Mips64And) \ |
| 32 V(Mips64Or) \ |
| 33 V(Mips64Xor) \ |
| 34 V(Mips64Shl) \ |
| 35 V(Mips64Shr) \ |
| 36 V(Mips64Sar) \ |
| 37 V(Mips64Ext) \ |
| 38 V(Mips64Dext) \ |
| 39 V(Mips64Dshl) \ |
| 40 V(Mips64Dshr) \ |
| 41 V(Mips64Dsar) \ |
| 42 V(Mips64Ror) \ |
| 43 V(Mips64Dror) \ |
| 44 V(Mips64Mov) \ |
| 45 V(Mips64Tst) \ |
| 46 V(Mips64Tst32) \ |
| 47 V(Mips64Cmp) \ |
| 48 V(Mips64Cmp32) \ |
| 49 V(Mips64CmpD) \ |
| 50 V(Mips64AddD) \ |
| 51 V(Mips64SubD) \ |
| 52 V(Mips64MulD) \ |
| 53 V(Mips64DivD) \ |
| 54 V(Mips64ModD) \ |
| 55 V(Mips64SqrtD) \ |
| 56 V(Mips64FloorD) \ |
| 57 V(Mips64CeilD) \ |
| 58 V(Mips64RoundTruncateD) \ |
| 59 V(Mips64CvtSD) \ |
| 60 V(Mips64CvtDS) \ |
| 61 V(Mips64TruncWD) \ |
| 62 V(Mips64TruncUwD) \ |
| 63 V(Mips64CvtDW) \ |
| 64 V(Mips64CvtDUw) \ |
| 65 V(Mips64Lb) \ |
| 66 V(Mips64Lbu) \ |
| 67 V(Mips64Sb) \ |
| 68 V(Mips64Lh) \ |
| 69 V(Mips64Lhu) \ |
| 70 V(Mips64Sh) \ |
| 71 V(Mips64Ld) \ |
| 72 V(Mips64Lw) \ |
| 73 V(Mips64Sw) \ |
| 74 V(Mips64Sd) \ |
| 75 V(Mips64Lwc1) \ |
| 76 V(Mips64Swc1) \ |
| 77 V(Mips64Ldc1) \ |
| 78 V(Mips64Sdc1) \ |
| 79 V(Mips64Push) \ |
| 80 V(Mips64StoreWriteBarrier) |
| 81 |
| 82 |
| 83 // Addressing modes represent the "shape" of inputs to an instruction. |
| 84 // Many instructions support multiple addressing modes. Addressing modes |
| 85 // are encoded into the InstructionCode of the instruction and tell the |
| 86 // code generator after register allocation which assembler method to call. |
| 87 // |
| 88 // We use the following local notation for addressing modes: |
| 89 // |
| 90 // R = register |
| 91 // O = register or stack slot |
| 92 // D = double register |
| 93 // I = immediate (handle, external, int32) |
| 94 // MRI = [register + immediate] |
| 95 // MRR = [register + register] |
| 96 // TODO(plind): Add the new r6 address modes. |
| 97 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
| 98 V(MRI) /* [%r0 + K] */ \ |
| 99 V(MRR) /* [%r0 + %r1] */ |
| 100 |
| 101 |
| 102 } // namespace compiler |
| 103 } // namespace internal |
| 104 } // namespace v8 |
| 105 |
| 106 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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Chromium Code Reviews
Issue 732403002:
MIPS64: Add turbofan support for mips64. (Closed)
Base URL: https://chromium.googlesource.com/v8/v8.git@master