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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 730183005: [turbofan] Recognize sign extension of 8-bit and 16-bit values on arm64. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 6 years ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 47 matching lines...) Expand 10 before | Expand all | Expand 10 after
58 V(Arm64Neg32) \ 58 V(Arm64Neg32) \
59 V(Arm64Lsl) \ 59 V(Arm64Lsl) \
60 V(Arm64Lsl32) \ 60 V(Arm64Lsl32) \
61 V(Arm64Lsr) \ 61 V(Arm64Lsr) \
62 V(Arm64Lsr32) \ 62 V(Arm64Lsr32) \
63 V(Arm64Asr) \ 63 V(Arm64Asr) \
64 V(Arm64Asr32) \ 64 V(Arm64Asr32) \
65 V(Arm64Ror) \ 65 V(Arm64Ror) \
66 V(Arm64Ror32) \ 66 V(Arm64Ror32) \
67 V(Arm64Mov32) \ 67 V(Arm64Mov32) \
68 V(Arm64Sxtb32) \
69 V(Arm64Sxth32) \
68 V(Arm64Sxtw) \ 70 V(Arm64Sxtw) \
69 V(Arm64Ubfx) \ 71 V(Arm64Ubfx) \
70 V(Arm64Ubfx32) \ 72 V(Arm64Ubfx32) \
71 V(Arm64Tbz) \ 73 V(Arm64Tbz) \
72 V(Arm64Tbz32) \ 74 V(Arm64Tbz32) \
73 V(Arm64Tbnz) \ 75 V(Arm64Tbnz) \
74 V(Arm64Tbnz32) \ 76 V(Arm64Tbnz32) \
75 V(Arm64Cbz32) \ 77 V(Arm64Cbz32) \
76 V(Arm64Cbnz32) \ 78 V(Arm64Cbnz32) \
77 V(Arm64Claim) \ 79 V(Arm64Claim) \
(...skipping 53 matching lines...) Expand 10 before | Expand all | Expand 10 after
131 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 133 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
132 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 134 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
133 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 135 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
134 V(Operand2_R_ROR_I) /* %r0 ROR K */ 136 V(Operand2_R_ROR_I) /* %r0 ROR K */
135 137
136 } // namespace internal 138 } // namespace internal
137 } // namespace compiler 139 } // namespace compiler
138 } // namespace v8 140 } // namespace v8
139 141
140 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 142 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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