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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 709123005: [arm] Recognize SXTB, SXTH, UXTB and UXTH. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 17 matching lines...) Expand all
28 V(ArmMls) \ 28 V(ArmMls) \
29 V(ArmSmmul) \ 29 V(ArmSmmul) \
30 V(ArmSmmla) \ 30 V(ArmSmmla) \
31 V(ArmUmull) \ 31 V(ArmUmull) \
32 V(ArmSdiv) \ 32 V(ArmSdiv) \
33 V(ArmUdiv) \ 33 V(ArmUdiv) \
34 V(ArmMov) \ 34 V(ArmMov) \
35 V(ArmMvn) \ 35 V(ArmMvn) \
36 V(ArmBfc) \ 36 V(ArmBfc) \
37 V(ArmUbfx) \ 37 V(ArmUbfx) \
38 V(ArmSxtb) \
39 V(ArmSxth) \
40 V(ArmSxtab) \
41 V(ArmSxtah) \
42 V(ArmUxtb) \
43 V(ArmUxth) \
44 V(ArmUxtab) \
45 V(ArmUxtah) \
38 V(ArmVcmpF64) \ 46 V(ArmVcmpF64) \
39 V(ArmVaddF64) \ 47 V(ArmVaddF64) \
40 V(ArmVsubF64) \ 48 V(ArmVsubF64) \
41 V(ArmVmulF64) \ 49 V(ArmVmulF64) \
42 V(ArmVmlaF64) \ 50 V(ArmVmlaF64) \
43 V(ArmVmlsF64) \ 51 V(ArmVmlsF64) \
44 V(ArmVdivF64) \ 52 V(ArmVdivF64) \
45 V(ArmVmodF64) \ 53 V(ArmVmodF64) \
46 V(ArmVnegF64) \ 54 V(ArmVnegF64) \
47 V(ArmVsqrtF64) \ 55 V(ArmVsqrtF64) \
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
87 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 95 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
88 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 96 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
89 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 97 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
90 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 98 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
91 99
92 } // namespace compiler 100 } // namespace compiler
93 } // namespace internal 101 } // namespace internal
94 } // namespace v8 102 } // namespace v8
95 103
96 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 104 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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