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1 // Copyright 2011 the V8 project authors. All rights reserved. | 1 // Copyright 2011 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1020 case 3: | 1020 case 3: |
1021 Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat"); | 1021 Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat"); |
1022 break; | 1022 break; |
1023 } | 1023 } |
1024 } else { | 1024 } else { |
1025 switch (instr->Bits(22, 21)) { | 1025 switch (instr->Bits(22, 21)) { |
1026 case 0: | 1026 case 0: |
1027 UNREACHABLE(); | 1027 UNREACHABLE(); |
1028 break; | 1028 break; |
1029 case 1: | 1029 case 1: |
1030 UNREACHABLE(); | 1030 if (instr->Bits(9, 6) == 1) { |
| 1031 if (instr->Bit(20) == 0) { |
| 1032 if (instr->Bits(19, 16) == 0xF) { |
| 1033 switch (instr->Bits(11, 10)) { |
| 1034 case 0: |
| 1035 Format(instr, "sxtb'cond 'rd, 'rm"); |
| 1036 break; |
| 1037 case 1: |
| 1038 Format(instr, "sxtb'cond 'rd, 'rm, ror #8"); |
| 1039 break; |
| 1040 case 2: |
| 1041 Format(instr, "sxtb'cond 'rd, 'rm, ror #16"); |
| 1042 break; |
| 1043 case 3: |
| 1044 Format(instr, "sxtb'cond 'rd, 'rm, ror #24"); |
| 1045 break; |
| 1046 } |
| 1047 } else { |
| 1048 switch (instr->Bits(11, 10)) { |
| 1049 case 0: |
| 1050 Format(instr, "sxtab'cond 'rd, 'rn, 'rm"); |
| 1051 break; |
| 1052 case 1: |
| 1053 Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #8"); |
| 1054 break; |
| 1055 case 2: |
| 1056 Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #16"); |
| 1057 break; |
| 1058 case 3: |
| 1059 Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #24"); |
| 1060 break; |
| 1061 } |
| 1062 } |
| 1063 } else { |
| 1064 if (instr->Bits(19, 16) == 0xF) { |
| 1065 switch (instr->Bits(11, 10)) { |
| 1066 case 0: |
| 1067 Format(instr, "sxth'cond 'rd, 'rm"); |
| 1068 break; |
| 1069 case 1: |
| 1070 Format(instr, "sxth'cond 'rd, 'rm, ror #8"); |
| 1071 break; |
| 1072 case 2: |
| 1073 Format(instr, "sxth'cond 'rd, 'rm, ror #16"); |
| 1074 break; |
| 1075 case 3: |
| 1076 Format(instr, "sxth'cond 'rd, 'rm, ror #24"); |
| 1077 break; |
| 1078 } |
| 1079 } else { |
| 1080 switch (instr->Bits(11, 10)) { |
| 1081 case 0: |
| 1082 Format(instr, "sxtah'cond 'rd, 'rn, 'rm"); |
| 1083 break; |
| 1084 case 1: |
| 1085 Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #8"); |
| 1086 break; |
| 1087 case 2: |
| 1088 Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #16"); |
| 1089 break; |
| 1090 case 3: |
| 1091 Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #24"); |
| 1092 break; |
| 1093 } |
| 1094 } |
| 1095 } |
| 1096 } else { |
| 1097 UNREACHABLE(); |
| 1098 } |
1031 break; | 1099 break; |
1032 case 2: | 1100 case 2: |
1033 if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) { | 1101 if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) { |
1034 if (instr->Bits(19, 16) == 0xF) { | 1102 if (instr->Bits(19, 16) == 0xF) { |
1035 switch (instr->Bits(11, 10)) { | 1103 switch (instr->Bits(11, 10)) { |
1036 case 0: | 1104 case 0: |
1037 Format(instr, "uxtb16'cond 'rd, 'rm"); | 1105 Format(instr, "uxtb16'cond 'rd, 'rm"); |
1038 break; | 1106 break; |
1039 case 1: | 1107 case 1: |
1040 Format(instr, "uxtb16'cond 'rd, 'rm, ror #8"); | 1108 Format(instr, "uxtb16'cond 'rd, 'rm, ror #8"); |
1041 break; | 1109 break; |
1042 case 2: | 1110 case 2: |
1043 Format(instr, "uxtb16'cond 'rd, 'rm, ror #16"); | 1111 Format(instr, "uxtb16'cond 'rd, 'rm, ror #16"); |
1044 break; | 1112 break; |
1045 case 3: | 1113 case 3: |
1046 Format(instr, "uxtb16'cond 'rd, 'rm, ror #24"); | 1114 Format(instr, "uxtb16'cond 'rd, 'rm, ror #24"); |
1047 break; | 1115 break; |
1048 } | 1116 } |
1049 } else { | 1117 } else { |
1050 UNREACHABLE(); | 1118 UNREACHABLE(); |
1051 } | 1119 } |
1052 } else { | 1120 } else { |
1053 UNREACHABLE(); | 1121 UNREACHABLE(); |
1054 } | 1122 } |
1055 break; | 1123 break; |
1056 case 3: | 1124 case 3: |
1057 if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) { | 1125 if ((instr->Bits(9, 6) == 1)) { |
1058 if (instr->Bits(19, 16) == 0xF) { | 1126 if ((instr->Bit(20) == 0)) { |
1059 switch (instr->Bits(11, 10)) { | 1127 if (instr->Bits(19, 16) == 0xF) { |
1060 case 0: | 1128 switch (instr->Bits(11, 10)) { |
1061 Format(instr, "uxtb'cond 'rd, 'rm"); | 1129 case 0: |
1062 break; | 1130 Format(instr, "uxtb'cond 'rd, 'rm"); |
1063 case 1: | 1131 break; |
1064 Format(instr, "uxtb'cond 'rd, 'rm, ror #8"); | 1132 case 1: |
1065 break; | 1133 Format(instr, "uxtb'cond 'rd, 'rm, ror #8"); |
1066 case 2: | 1134 break; |
1067 Format(instr, "uxtb'cond 'rd, 'rm, ror #16"); | 1135 case 2: |
1068 break; | 1136 Format(instr, "uxtb'cond 'rd, 'rm, ror #16"); |
1069 case 3: | 1137 break; |
1070 Format(instr, "uxtb'cond 'rd, 'rm, ror #24"); | 1138 case 3: |
1071 break; | 1139 Format(instr, "uxtb'cond 'rd, 'rm, ror #24"); |
| 1140 break; |
| 1141 } |
| 1142 } else { |
| 1143 switch (instr->Bits(11, 10)) { |
| 1144 case 0: |
| 1145 Format(instr, "uxtab'cond 'rd, 'rn, 'rm"); |
| 1146 break; |
| 1147 case 1: |
| 1148 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #8"); |
| 1149 break; |
| 1150 case 2: |
| 1151 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #16"); |
| 1152 break; |
| 1153 case 3: |
| 1154 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #24"); |
| 1155 break; |
| 1156 } |
1072 } | 1157 } |
1073 } else { | 1158 } else { |
1074 switch (instr->Bits(11, 10)) { | 1159 if (instr->Bits(19, 16) == 0xF) { |
1075 case 0: | 1160 switch (instr->Bits(11, 10)) { |
1076 Format(instr, "uxtab'cond 'rd, 'rn, 'rm"); | 1161 case 0: |
1077 break; | 1162 Format(instr, "uxth'cond 'rd, 'rm"); |
1078 case 1: | 1163 break; |
1079 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #8"); | 1164 case 1: |
1080 break; | 1165 Format(instr, "uxth'cond 'rd, 'rm, ror #8"); |
1081 case 2: | 1166 break; |
1082 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #16"); | 1167 case 2: |
1083 break; | 1168 Format(instr, "uxth'cond 'rd, 'rm, ror #16"); |
1084 case 3: | 1169 break; |
1085 Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #24"); | 1170 case 3: |
1086 break; | 1171 Format(instr, "uxth'cond 'rd, 'rm, ror #24"); |
| 1172 break; |
| 1173 } |
| 1174 } else { |
| 1175 switch (instr->Bits(11, 10)) { |
| 1176 case 0: |
| 1177 Format(instr, "uxtah'cond 'rd, 'rn, 'rm"); |
| 1178 break; |
| 1179 case 1: |
| 1180 Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #8"); |
| 1181 break; |
| 1182 case 2: |
| 1183 Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #16"); |
| 1184 break; |
| 1185 case 3: |
| 1186 Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #24"); |
| 1187 break; |
| 1188 } |
1087 } | 1189 } |
1088 } | 1190 } |
1089 } else { | 1191 } else { |
1090 UNREACHABLE(); | 1192 UNREACHABLE(); |
1091 } | 1193 } |
1092 break; | 1194 break; |
1093 } | 1195 } |
1094 } | 1196 } |
1095 } | 1197 } |
1096 break; | 1198 break; |
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1844 v8::internal::PrintF( | 1946 v8::internal::PrintF( |
1845 f, "%p %08x %s\n", | 1947 f, "%p %08x %s\n", |
1846 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1948 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1847 } | 1949 } |
1848 } | 1950 } |
1849 | 1951 |
1850 | 1952 |
1851 } // namespace disasm | 1953 } // namespace disasm |
1852 | 1954 |
1853 #endif // V8_TARGET_ARCH_ARM | 1955 #endif // V8_TARGET_ARCH_ARM |
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