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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// | 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // This file implements the TargetLoweringX8632 class, which | 10 // This file implements the TargetLoweringX8632 class, which |
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4177 } // end of anonymous namespace | 4177 } // end of anonymous namespace |
4178 | 4178 |
4179 // Lower the pre-ordered list of assignments into mov instructions. | 4179 // Lower the pre-ordered list of assignments into mov instructions. |
4180 // Also has to do some ad-hoc register allocation as necessary. | 4180 // Also has to do some ad-hoc register allocation as necessary. |
4181 void TargetX8632::lowerPhiAssignments(CfgNode *Node, | 4181 void TargetX8632::lowerPhiAssignments(CfgNode *Node, |
4182 const AssignList &Assignments) { | 4182 const AssignList &Assignments) { |
4183 // Check that this is a properly initialized shell of a node. | 4183 // Check that this is a properly initialized shell of a node. |
4184 assert(Node->getOutEdges().size() == 1); | 4184 assert(Node->getOutEdges().size() == 1); |
4185 assert(Node->getInsts().empty()); | 4185 assert(Node->getInsts().empty()); |
4186 assert(Node->getPhis().empty()); | 4186 assert(Node->getPhis().empty()); |
4187 CfgNode *Succ = Node->getOutEdges()[0]; | 4187 CfgNode *Succ = Node->getOutEdges().front(); |
4188 getContext().init(Node); | 4188 getContext().init(Node); |
4189 // Register set setup similar to regAlloc() and postLower(). | 4189 // Register set setup similar to regAlloc() and postLower(). |
4190 RegSetMask RegInclude = RegSet_All; | 4190 RegSetMask RegInclude = RegSet_All; |
4191 RegSetMask RegExclude = RegSet_StackPointer; | 4191 RegSetMask RegExclude = RegSet_StackPointer; |
4192 if (hasFramePointer()) | 4192 if (hasFramePointer()) |
4193 RegExclude |= RegSet_FramePointer; | 4193 RegExclude |= RegSet_FramePointer; |
4194 llvm::SmallBitVector Available = getRegisterSet(RegInclude, RegExclude); | 4194 llvm::SmallBitVector Available = getRegisterSet(RegInclude, RegExclude); |
4195 bool NeedsRegs = false; | 4195 bool NeedsRegs = false; |
4196 // Initialize the set of available registers to the set of what is | 4196 // Initialize the set of available registers to the set of what is |
4197 // available (not live) at the beginning of the successor block, | 4197 // available (not live) at the beginning of the successor block, |
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4724 } else if (IsConstant || IsExternal) | 4724 } else if (IsConstant || IsExternal) |
4725 Str << "\t.zero\t" << Size << "\n"; | 4725 Str << "\t.zero\t" << Size << "\n"; |
4726 // Size is part of .comm. | 4726 // Size is part of .comm. |
4727 | 4727 |
4728 if (IsConstant || HasNonzeroInitializer || IsExternal) | 4728 if (IsConstant || HasNonzeroInitializer || IsExternal) |
4729 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; | 4729 Str << "\t.size\t" << MangledName << ", " << Size << "\n"; |
4730 // Size is part of .comm. | 4730 // Size is part of .comm. |
4731 } | 4731 } |
4732 | 4732 |
4733 } // end of namespace Ice | 4733 } // end of namespace Ice |
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