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Issue 704543002: ARM: optimize inlined doubles (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 1 month ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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2538 vldr(dst, MemOperand(pp, ip)); 2538 vldr(dst, MemOperand(pp, ip));
2539 } else { 2539 } else {
2540 DCHECK(section == ConstantPoolArray::SMALL_SECTION); 2540 DCHECK(section == ConstantPoolArray::SMALL_SECTION);
2541 vldr(dst, MemOperand(FLAG_enable_ool_constant_pool ? pp : pc, 0)); 2541 vldr(dst, MemOperand(FLAG_enable_ool_constant_pool ? pp : pc, 0));
2542 } 2542 }
2543 } else { 2543 } else {
2544 // Synthesise the double from ARM immediates. 2544 // Synthesise the double from ARM immediates.
2545 uint32_t lo, hi; 2545 uint32_t lo, hi;
2546 DoubleAsTwoUInt32(imm, &lo, &hi); 2546 DoubleAsTwoUInt32(imm, &lo, &hi);
2547 2547
2548 if (scratch.is(no_reg)) { 2548 if (lo == hi) {
2549 if (dst.code() < 16) { 2549 // Move the low and high parts of the double to a D register in one
2550 const LowDwVfpRegister loc = LowDwVfpRegister::from_code(dst.code()); 2550 // instruction.
2551 // Move the low part of the double into the lower of the corresponsing S 2551 mov(ip, Operand(lo));
2552 // registers of D register dst. 2552 vmov(dst, ip, ip);
2553 mov(ip, Operand(lo)); 2553 } else if (scratch.is(no_reg)) {
2554 vmov(loc.low(), ip); 2554 mov(ip, Operand(lo));
2555 2555 vmov(dst, VmovIndexLo, ip);
2556 // Move the high part of the double into the higher of the 2556 if ((lo & 0xffff) == (hi & 0xffff)) {
2557 // corresponsing S registers of D register dst. 2557 movt(ip, hi >> 16);
2558 } else {
2558 mov(ip, Operand(hi)); 2559 mov(ip, Operand(hi));
2559 vmov(loc.high(), ip);
2560 } else {
2561 // D16-D31 does not have S registers, so move the low and high parts
2562 // directly to the D register using vmov.32.
2563 // Note: This may be slower, so we only do this when we have to.
2564 mov(ip, Operand(lo));
2565 vmov(dst, VmovIndexLo, ip);
2566 mov(ip, Operand(hi));
2567 vmov(dst, VmovIndexHi, ip);
2568 } 2560 }
2561 vmov(dst, VmovIndexHi, ip);
2569 } else { 2562 } else {
2570 // Move the low and high parts of the double to a D register in one 2563 // Move the low and high parts of the double to a D register in one
2571 // instruction. 2564 // instruction.
2572 mov(ip, Operand(lo)); 2565 mov(ip, Operand(lo));
2573 mov(scratch, Operand(hi)); 2566 mov(scratch, Operand(hi));
2574 vmov(dst, ip, scratch); 2567 vmov(dst, ip, scratch);
2575 } 2568 }
2576 } 2569 }
2577 } 2570 }
2578 2571
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3924 assm->instr_at_put( 3917 assm->instr_at_put(
3925 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset)); 3918 rinfo.pc(), Assembler::SetLdrRegisterImmediateOffset(instr, offset));
3926 } 3919 }
3927 } 3920 }
3928 } 3921 }
3929 3922
3930 3923
3931 } } // namespace v8::internal 3924 } } // namespace v8::internal
3932 3925
3933 #endif // V8_TARGET_ARCH_ARM 3926 #endif // V8_TARGET_ARCH_ARM
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