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Issue 701543002: MIPS: [turbofan] Also optimize unsigned division by constant. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 1 month ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> // For LONG_MIN, LONG_MAX. 5 #include <limits.h> // For LONG_MIN, LONG_MAX.
6 6
7 #include "src/v8.h" 7 #include "src/v8.h"
8 8
9 #if V8_TARGET_ARCH_MIPS 9 #if V8_TARGET_ARCH_MIPS
10 10
(...skipping 722 matching lines...) Expand 10 before | Expand all | Expand 10 after
733 mult(rs, rt.rm()); 733 mult(rs, rt.rm());
734 } else { 734 } else {
735 // li handles the relocation. 735 // li handles the relocation.
736 DCHECK(!rs.is(at)); 736 DCHECK(!rs.is(at));
737 li(at, rt); 737 li(at, rt);
738 mult(rs, at); 738 mult(rs, at);
739 } 739 }
740 } 740 }
741 741
742 742
743 void MacroAssembler::Mulhu(Register rd, Register rs, const Operand& rt) {
744 if (rt.is_reg()) {
745 if (!IsMipsArchVariant(kMips32r6)) {
746 multu(rs, rt.rm());
747 mfhi(rd);
748 } else {
749 muhu(rd, rs, rt.rm());
750 }
751 } else {
752 // li handles the relocation.
753 DCHECK(!rs.is(at));
754 li(at, rt);
755 if (!IsMipsArchVariant(kMips32r6)) {
756 multu(rs, at);
757 mfhi(rd);
758 } else {
759 muhu(rd, rs, at);
760 }
761 }
762 }
763
764
743 void MacroAssembler::Multu(Register rs, const Operand& rt) { 765 void MacroAssembler::Multu(Register rs, const Operand& rt) {
744 if (rt.is_reg()) { 766 if (rt.is_reg()) {
745 multu(rs, rt.rm()); 767 multu(rs, rt.rm());
746 } else { 768 } else {
747 // li handles the relocation. 769 // li handles the relocation.
748 DCHECK(!rs.is(at)); 770 DCHECK(!rs.is(at));
749 li(at, rt); 771 li(at, rt);
750 multu(rs, at); 772 multu(rs, at);
751 } 773 }
752 } 774 }
(...skipping 5469 matching lines...) Expand 10 before | Expand all | Expand 10 after
6222 } 6244 }
6223 if (mag.shift > 0) sra(result, result, mag.shift); 6245 if (mag.shift > 0) sra(result, result, mag.shift);
6224 srl(at, dividend, 31); 6246 srl(at, dividend, 31);
6225 Addu(result, result, Operand(at)); 6247 Addu(result, result, Operand(at));
6226 } 6248 }
6227 6249
6228 6250
6229 } } // namespace v8::internal 6251 } } // namespace v8::internal
6230 6252
6231 #endif // V8_TARGET_ARCH_MIPS 6253 #endif // V8_TARGET_ARCH_MIPS
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