Implement bigint intrinsics on arm64.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 657 matching lines @@
   }
   void madd(Register rd, Register rn, Register rm, Register ra) {
     EmitMiscDP3Source(MADD, rd, rn, rm, ra, kDoubleWord);
   }
   void msub(Register rd, Register rn, Register rm, Register ra) {
     EmitMiscDP3Source(MSUB, rd, rn, rm, ra, kDoubleWord);
   }
   void smulh(Register rd, Register rn, Register rm) {
     EmitMiscDP3Source(SMULH, rd, rn, rm, R0, kDoubleWord);
   }
+  void umaddl(Register rd, Register rn, Register rm, Register ra) {
+    EmitMiscDP3Source(UMADDL, rd, rn, rm, ra, kDoubleWord);
+  }
 
   // Move wide immediate.
   void movk(Register rd, const Immediate& imm, int hw_idx) {
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVK, crd, imm, hw_idx, kDoubleWord);
   }
   void movn(Register rd, const Immediate& imm, int hw_idx) {
     ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
@@ skipping 87 matching lines @@
       // UXTX 0 on a 64-bit register (rm) is a nop, but forces R31 to be
       // interpreted as CSP.
       cmp(CSP, Operand(rm, UXTX, 0));
     } else {
       cmp(rn, Operand(rm));
     }
   }
 
   // Conditional branch.
   void b(Label* label, Condition cond = AL) {
-    EmitBranch(BCOND, cond, label);
+    EmitConditionalBranch(BCOND, cond, label);
   }
 
   void b(int32_t offset) {
     EmitUnconditionalBranchOp(B, offset);
   }
   void bl(int32_t offset) {
     EmitUnconditionalBranchOp(BL, offset);
   }
 
-  // TODO(zra): cbz, cbnz.
+  void cbz(Label* label, Register rt, OperandSize sz = kDoubleWord) {
+    EmitCompareAndBranch(CBZ, rt, label, sz);
+  }
+
+  void cbnz(Label* label, Register rt, OperandSize sz = kDoubleWord) {
+    EmitCompareAndBranch(CBNZ, rt, label, sz);
+  }
 
   // Branch, link, return.
   void br(Register rn) {
     EmitUnconditionalBranchRegOp(BR, rn);
   }
   void blr(Register rn) {
     EmitUnconditionalBranchRegOp(BLR, rn);
   }
   void ret(Register rn = R30) {
     EmitUnconditionalBranchRegOp(RET, rn);
@@ skipping 787 matching lines @@
     const int32_t imm32 = static_cast<int32_t>(imm);
     const int32_t off = (((imm32 >> 2) << kImm26Shift) & kImm26Mask);
     return (instr & ~kImm26Mask) | off;
   }
 
   int64_t DecodeImm26BranchOffset(int32_t instr) {
     const int32_t off = (((instr & kImm26Mask) >> kImm26Shift) << 6) >> 4;
     return static_cast<int64_t>(off);
   }
 
-  void EmitCompareAndBranch(CompareAndBranchOp op, Register rt, int64_t imm,
-                            OperandSize sz) {
+  void EmitCompareAndBranchOp(CompareAndBranchOp op, Register rt, int64_t imm,
+                              OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
     ASSERT((rt != CSP) && (rt != R31));
     const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoded_offset = EncodeImm19BranchOffset(imm, 0);
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crt) << kRtShift) |
         encoded_offset;
     Emit(encoding);
   }
 
-  void EmitConditionalBranch(ConditionalBranchOp op, Condition cond,
-                             int64_t imm) {
+  void EmitConditionalBranchOp(ConditionalBranchOp op, Condition cond,
+                               int64_t imm) {
     const int32_t off = EncodeImm19BranchOffset(imm, 0);
     const int32_t encoding =
         op |
         (static_cast<int32_t>(cond) << kCondShift) |
         off;
     Emit(encoding);
   }
 
   bool CanEncodeImm19BranchOffset(int64_t offset) {
     ASSERT(Utils::IsAligned(offset, 4));
     return Utils::IsInt(21, offset);
   }
 
-  void EmitBranch(ConditionalBranchOp op, Condition cond, Label* label) {
+  void EmitConditionalBranch(ConditionalBranchOp op, Condition cond,
+                             Label* label) {
     if (label->IsBound()) {
       const int64_t dest = label->Position() - buffer_.Size();
       if (use_far_branches() && !CanEncodeImm19BranchOffset(dest)) {
         if (cond == AL) {
           // If the condition is AL, we must always branch to dest. There is
           // no need for a guard branch.
           b(dest);
         } else {
-          EmitConditionalBranch(
+          EmitConditionalBranchOp(
               op, InvertCondition(cond), 2 * Instr::kInstrSize);
           b(dest);
         }
       } else {
-        EmitConditionalBranch(op, cond, dest);
+        EmitConditionalBranchOp(op, cond, dest);
       }
     } else {
       const int64_t position = buffer_.Size();
       if (use_far_branches()) {
         // When cond is AL, this guard branch will be rewritten as a nop when
         // the label is bound. We don't write it as a nop initially because it
         // makes the decoding code in Bind simpler.
-        EmitConditionalBranch(op, InvertCondition(cond), 2 * Instr::kInstrSize);
+        EmitConditionalBranchOp(
+            op, InvertCondition(cond), 2 * Instr::kInstrSize);
         b(label->position_);
       } else {
-        EmitConditionalBranch(op, cond, label->position_);
+        EmitConditionalBranchOp(op, cond, label->position_);
+      }
+      label->LinkTo(position);
+    }
+  }
+
+  void EmitCompareAndBranch(CompareAndBranchOp op, Register rt,

[zra, 2014/11/06 00:30:59]

You also need to detect these instructions in Bind in assembler_arm64.cc and
make the right fixups.

+                            Label* label, OperandSize sz) {
+    if (label->IsBound()) {
+      const int64_t dest = label->Position() - buffer_.Size();
+      if (use_far_branches() && !CanEncodeImm19BranchOffset(dest)) {
+          EmitCompareAndBranchOp(
+              op == CBZ ? CBNZ : CBZ, rt, 2 * Instr::kInstrSize, sz);
+          b(dest);
+      } else {
+        EmitCompareAndBranchOp(op, rt, dest, sz);
+      }
+    } else {
+      const int64_t position = buffer_.Size();
+      if (use_far_branches()) {
+        EmitCompareAndBranchOp(
+            op == CBZ ? CBNZ : CBZ, rt, 2 * Instr::kInstrSize, sz);
+        b(label->position_);
+      } else {
+        EmitCompareAndBranchOp(op, rt, label->position_, sz);
       }
       label->LinkTo(position);
     }
   }
 
   bool CanEncodeImm26BranchOffset(int64_t offset) {
     ASSERT(Utils::IsAligned(offset, 4));
     return Utils::IsInt(26, offset);
   }
 
@@ skipping 229 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_