More consistently use auto for emit*, nullptr in asm code.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 332 matching lines @@
 // ======================== Dump routines ======================== //
 
 namespace {
 
 void emitIASBytes(const Cfg *Func, const x86::AssemblerX86 *Asm,
                   intptr_t StartPosition) {
   GlobalContext *Ctx = Func->getContext();
   Ostream &Str = Ctx->getStrEmit();
   intptr_t EndPosition = Asm->GetPosition();
   AssemblerFixup *LastFixup = Asm->GetLatestFixup(StartPosition);
-  if (LastFixup == NULL) {
+  if (!LastFixup) {
     // The fixup doesn't apply to this current block.
     for (intptr_t i = StartPosition; i < EndPosition; ++i) {
       Str << "\t.byte 0x";
       Str.write_hex(Asm->LoadBuffer<uint8_t>(i));
       Str << "\n";
     }
     return;
   }
   intptr_t LastFixupLoc = LastFixup->position();
   const intptr_t FixupSize = 4;
@@ skipping 11 matching lines @@
     else
       Str << Ctx->mangleName(Reloc->getName());
     if (LastFixup->value()->getOffset()) {
       Str << " + " << LastFixup->value()->getOffset();
     }
     Str << "\n";
     LastFixupLoc += FixupSize;
     assert(LastFixupLoc <= EndPosition);
     LastFixup = Asm->GetLatestFixup(LastFixupLoc);
     // Assume multi-fixups are adjacent in the instruction encoding.
-    assert(LastFixup == NULL || LastFixup->position() == LastFixupLoc);
+    assert(!LastFixup || LastFixup->position() == LastFixupLoc);
   }
   for (intptr_t i = LastFixupLoc; i < EndPosition; ++i) {
     Str << "\t.byte 0x";
     Str.write_hex(Asm->LoadBuffer<uint8_t>(i));
     Str << "\n";
   }
 }
 
 void emitIASBytesBranch(const Cfg *Func, const x86::AssemblerX86 *Asm,
                         intptr_t StartPosition, const x86::Label *Label,
@@ skipping 132 matching lines @@
     if (getTargetFalse()) {
       Str << ", label %" << getTargetFalse()->getName();
     }
   }
 }
 
 void InstX8632Call::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\tcall\t";
-  if (auto CallTarget = llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
+  if (const auto CallTarget =
+          llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
     // TODO(stichnot): All constant targets should suppress the '$',
     // not just relocatables.
     CallTarget->emitWithoutDollar(Func->getContext());
   } else {
     Str << "*";
     getCallTarget()->emit(Func);
   }
   Func->getTarget()->resetStackAdjustment();
 }
 
@@ skipping 59 matching lines @@
 // Opcode parameter needs to be char* and not IceString because of
 // template issues.
 void emitTwoAddress(const char *Opcode, const Inst *Inst, const Cfg *Func,
                     bool ShiftHack) {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
   Variable *Dest = Inst->getDest();
   assert(Dest == Inst->getSrc(0));
   Operand *Src1 = Inst->getSrc(1);
   Str << "\t" << Opcode << InstX8632::getWidthString(Dest->getType()) << "\t";
-  Variable *ShiftReg = llvm::dyn_cast<Variable>(Src1);
+  const auto ShiftReg = llvm::dyn_cast<Variable>(Src1);
   if (ShiftHack && ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx)
     Str << "%cl";
   else
     Src1->emit(Func);
   Str << ", ";
   Dest->emit(Func);
 }
 
 void emitIASOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op,
                     const x86::AssemblerX86::GPREmitterOneOp &Emitter) {
@@ skipping 128 matching lines @@
 }
 
 void emitIASGPRShiftDouble(const Cfg *Func, const Variable *Dest,
                            const Operand *Src1Op, const Operand *Src2Op,
                            const x86::AssemblerX86::GPREmitterShiftD &Emitter) {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   // Dest can be reg or mem, but we only use the reg variant.
   assert(Dest->hasReg());
   RegX8632::GPRRegister DestReg = RegX8632::getEncodedGPR(Dest->getRegNum());
-  // Src1 must be reg.
-  const auto Src1 = llvm::cast<Variable>(Src1Op);
-  assert(Src1->hasReg());
-  RegX8632::GPRRegister SrcReg = RegX8632::getEncodedGPR(Src1->getRegNum());
-  Type Ty = Src1->getType();
+  // SrcVar1 must be reg.
+  const auto SrcVar1 = llvm::cast<Variable>(Src1Op);
+  assert(SrcVar1->hasReg());
+  RegX8632::GPRRegister SrcReg = RegX8632::getEncodedGPR(SrcVar1->getRegNum());
+  Type Ty = SrcVar1->getType();
   // Src2 can be the implicit CL register or an immediate.
   if (const auto Imm = llvm::dyn_cast<ConstantInteger32>(Src2Op)) {
     (Asm->*(Emitter.GPRGPRImm))(Ty, DestReg, SrcReg,
                                 x86::Immediate(Imm->getValue()));
   } else {
     assert(llvm::cast<Variable>(Src2Op)->getRegNum() == RegX8632::Reg_ecx);
     (Asm->*(Emitter.GPRGPR))(Ty, DestReg, SrcReg);
   }
   emitIASBytes(Func, Asm, StartPosition);
 }
@@ skipping 132 matching lines @@
     } else if (const auto SrcMem = llvm::dyn_cast<OperandX8632Mem>(Src)) {
       assert(SrcMem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
       (Asm->*(Emitter.XmmAddr))(DestReg, SrcMem->toAsmAddress(Asm));
     } else {
       llvm_unreachable("Unexpected operand type");
     }
   } else {
     x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget())
                                ->stackVarToAsmOperand(Dest));
     // Src must be a register in this case.
-    const Variable *SrcVar = llvm::cast<Variable>(Src);
+    const auto SrcVar = llvm::cast<Variable>(Src);
     assert(SrcVar->hasReg());
     (Asm->*(Emitter.AddrXmm))(StackAddr,
                               RegX8632::getEncodedXmm(SrcVar->getRegNum()));
   }
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 bool checkForRedundantAssign(const Variable *Dest, const Operand *Source) {
-  const Variable *Src = llvm::dyn_cast<const Variable>(Source);
-  if (Src == NULL)
+  const auto SrcVar = llvm::dyn_cast<const Variable>(Source);
+  if (!SrcVar)
     return false;
-  if (Dest->hasReg() && Dest->getRegNum() == Src->getRegNum()) {
+  if (Dest->hasReg() && Dest->getRegNum() == SrcVar->getRegNum()) {
     // TODO: On x86-64, instructions like "mov eax, eax" are used to
     // clear the upper 32 bits of rax.  We need to recognize and
     // preserve these.
     return true;
   }
-  if (!Dest->hasReg() && !Src->hasReg() &&
-      Dest->getStackOffset() == Src->getStackOffset())
+  if (!Dest->hasReg() && !SrcVar->hasReg() &&
+      Dest->getStackOffset() == SrcVar->getStackOffset())
     return true;
   return false;
 }
 
 // In-place ops
 template <> const char *InstX8632Bswap::Opcode = "bswap";
 template <> const char *InstX8632Neg::Opcode = "neg";
 // Unary ops
 template <> const char *InstX8632Bsf::Opcode = "bsf";
 template <> const char *InstX8632Bsr::Opcode = "bsr";
@@ skipping 49 matching lines @@
 template <> const char *InstX8632Pinsr::Opcode = "pinsr";
 template <> const char *InstX8632Blendvps::Opcode = "blendvps";
 template <> const char *InstX8632Pblendvb::Opcode = "pblendvb";
 // Three address ops
 template <> const char *InstX8632Pextr::Opcode = "pextr";
 template <> const char *InstX8632Pshufd::Opcode = "pshufd";
 
 // Inplace GPR ops
 template <>
 const x86::AssemblerX86::GPREmitterOneOp InstX8632Bswap::Emitter = {
-    &x86::AssemblerX86::bswap, NULL /* only a reg form exists */};
+    &x86::AssemblerX86::bswap, nullptr /* only a reg form exists */};
 template <>
 const x86::AssemblerX86::GPREmitterOneOp InstX8632Neg::Emitter = {
     &x86::AssemblerX86::neg, &x86::AssemblerX86::neg};
 
 // Unary GPR ops
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsf::Emitter = {
-    &x86::AssemblerX86::bsf, &x86::AssemblerX86::bsf, NULL};
+    &x86::AssemblerX86::bsf, &x86::AssemblerX86::bsf, nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Bsr::Emitter = {
-    &x86::AssemblerX86::bsr, &x86::AssemblerX86::bsr, NULL};
+    &x86::AssemblerX86::bsr, &x86::AssemblerX86::bsr, nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Lea::Emitter = {
-    /* reg/reg and reg/imm are illegal */ NULL, &x86::AssemblerX86::lea, NULL};
+    /* reg/reg and reg/imm are illegal */ nullptr, &x86::AssemblerX86::lea,
+    nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movsx::Emitter = {
-    &x86::AssemblerX86::movsx, &x86::AssemblerX86::movsx, NULL};
+    &x86::AssemblerX86::movsx, &x86::AssemblerX86::movsx, nullptr};
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Movzx::Emitter = {
-    &x86::AssemblerX86::movzx, &x86::AssemblerX86::movzx, NULL};
+    &x86::AssemblerX86::movzx, &x86::AssemblerX86::movzx, nullptr};
 
 // Unary XMM ops
 template <>
 const x86::AssemblerX86::XmmEmitterRegOp InstX8632Sqrtss::Emitter = {
   &x86::AssemblerX86::sqrtss, &x86::AssemblerX86::sqrtss
 };
 
 // Binary GPR ops
 template <>
 const x86::AssemblerX86::GPREmitterRegOp InstX8632Add::Emitter = {
@@ skipping 296 matching lines @@
       &x86::AssemblerX86::pblendvb, &x86::AssemblerX86::pblendvb};
   emitIASVariableBlendInst(this, Func, Emitter);
 }
 
 template <> void InstX8632Imul::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   Variable *Dest = getDest();
   if (isByteSizedArithType(Dest->getType())) {
     // The 8-bit version of imul only allows the form "imul r/m8".
-    Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
-    (void)Src0;
-    assert(Src0 && Src0->getRegNum() == RegX8632::Reg_eax);
+    const auto Src0Var = llvm::dyn_cast<Variable>(getSrc(0));
+    (void)Src0Var;
+    assert(Src0Var && Src0Var->getRegNum() == RegX8632::Reg_eax);
     Str << "\timulb\t";
     getSrc(1)->emit(Func);
   } else if (llvm::isa<Constant>(getSrc(1))) {
     Str << "\timul" << getWidthString(Dest->getType()) << "\t";
     getSrc(1)->emit(Func);
     Str << ", ";
     getSrc(0)->emit(Func);
     Str << ", ";
     Dest->emit(Func);
   } else {
     emitTwoAddress("imul", this, Func);
   }
 }
 
 template <> void InstX8632Imul::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Variable *Var = getDest();
   Type Ty = Var->getType();
   const Operand *Src = getSrc(1);
   if (isByteSizedArithType(Ty)) {
     // The 8-bit version of imul only allows the form "imul r/m8".
-    Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
-    (void)Src0;
-    assert(Src0 && Src0->getRegNum() == RegX8632::Reg_eax);
+    const auto Src0Var = llvm::dyn_cast<Variable>(getSrc(0));
+    (void)Src0Var;
+    assert(Src0Var && Src0Var->getRegNum() == RegX8632::Reg_eax);
     const x86::AssemblerX86::GPREmitterOneOp Emitter = {
         &x86::AssemblerX86::imul, &x86::AssemblerX86::imul};
     emitIASOpTyGPR(Func, Ty, getSrc(1), Emitter);
   } else {
     // We only use imul as a two-address instruction even though
     // there is a 3 operand version when one of the operands is a constant.
     assert(Var == getSrc(0));
     const x86::AssemblerX86::GPREmitterRegOp Emitter = {
         &x86::AssemblerX86::imul, &x86::AssemblerX86::imul,
         &x86::AssemblerX86::imul};
@@ skipping 65 matching lines @@
     Asm->cdq();
     break;
   }
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632Mul::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   assert(llvm::isa<Variable>(getSrc(0)));
-  assert(llvm::dyn_cast<Variable>(getSrc(0))->getRegNum() == RegX8632::Reg_eax);
+  assert(llvm::cast<Variable>(getSrc(0))->getRegNum() == RegX8632::Reg_eax);
   assert(getDest()->getRegNum() == RegX8632::Reg_eax); // TODO: allow edx?
   Str << "\tmul" << getWidthString(getDest()->getType()) << "\t";
   getSrc(1)->emit(Func);
 }
 
 void InstX8632Mul::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   assert(llvm::isa<Variable>(getSrc(0)));
-  assert(llvm::dyn_cast<Variable>(getSrc(0))->getRegNum() == RegX8632::Reg_eax);
+  assert(llvm::cast<Variable>(getSrc(0))->getRegNum() == RegX8632::Reg_eax);
   assert(getDest()->getRegNum() == RegX8632::Reg_eax); // TODO: allow edx?
   const Operand *Src = getSrc(1);
   Type Ty = Src->getType();
   const static x86::AssemblerX86::GPREmitterOneOp Emitter = {
       &x86::AssemblerX86::mul, &x86::AssemblerX86::mul};
   emitIASOpTyGPR(Func, Ty, Src, Emitter);
 }
 
 void InstX8632Mul::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = mul." << getDest()->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632Shld::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = getDest();
   assert(getSrcSize() == 3);
   assert(Dest == getSrc(0));
   Str << "\tshld" << getWidthString(Dest->getType()) << "\t";
-  if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+  if (const auto ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
     (void)ShiftReg;
     assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
     Str << "%cl";
   } else {
     getSrc(2)->emit(Func);
   }
   Str << ", ";
   getSrc(1)->emit(Func);
   Str << ", ";
   Dest->emit(Func);
@@ skipping 16 matching lines @@
   Str << " = shld." << getDest()->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632Shrd::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   Variable *Dest = getDest();
   assert(getSrcSize() == 3);
   assert(Dest == getSrc(0));
   Str << "\tshrd" << getWidthString(Dest->getType()) << "\t";
-  if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+  if (const auto ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
     (void)ShiftReg;
     assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
     Str << "%cl";
   } else {
     getSrc(2)->emit(Func);
   }
   Str << ", ";
   getSrc(1)->emit(Func);
   Str << ", ";
   Dest->emit(Func);
@@ skipping 28 matching lines @@
   getSrc(1)->emit(Func);
   Str << ", ";
   Dest->emit(Func);
 }
 
 void InstX8632Cmov::emitIAS(const Cfg *Func) const {
   assert(Condition != CondX86::Br_None);
   assert(getDest()->hasReg());
   assert(getSrcSize() == 2);
   // Only need the reg/reg form now.
-  const Variable *Src = llvm::cast<Variable>(getSrc(1));
-  assert(Src->hasReg());
-  assert(Src->getType() == IceType_i32);
+  const auto SrcVar = llvm::cast<Variable>(getSrc(1));
+  assert(SrcVar->hasReg());
+  assert(SrcVar->getType() == IceType_i32);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Asm->cmov(Condition, RegX8632::getEncodedGPR(getDest()->getRegNum()),
-            RegX8632::getEncodedGPR(Src->getRegNum()));
+            RegX8632::getEncodedGPR(SrcVar->getRegNum()));
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632Cmov::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "cmov" << InstX8632BrAttributes[Condition].DisplayString << ".";
   Str << getDest()->getType() << " ";
   dumpDest(Func);
   Str << ", ";
   dumpSources(Func);
@@ skipping 12 matching lines @@
 }
 
 void InstX8632Cmpps::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 2);
   assert(Condition < CondX86::Cmpps_Invalid);
   // Assuming there isn't any load folding for cmpps, and vector constants
   // are not allowed in PNaCl.
   assert(llvm::isa<Variable>(getSrc(1)));
-  const Variable *SrcVar = llvm::cast<Variable>(getSrc(1));
+  const auto SrcVar = llvm::cast<Variable>(getSrc(1));
   if (SrcVar->hasReg()) {
     Asm->cmpps(RegX8632::getEncodedXmm(getDest()->getRegNum()),
                RegX8632::getEncodedXmm(SrcVar->getRegNum()), Condition);
   } else {
     x86::Address SrcStackAddr = static_cast<TargetX8632 *>(Func->getTarget())
                                     ->stackVarToAsmOperand(SrcVar);
     Asm->cmpps(RegX8632::getEncodedXmm(getDest()->getRegNum()), SrcStackAddr,
                Condition);
   }
   emitIASBytes(Func, Asm, StartPosition);
@@ skipping 18 matching lines @@
   getSrc(2)->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Cmpxchg::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Type Ty = getSrc(0)->getType();
-  const OperandX8632Mem *Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
+  const auto Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
   assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   const x86::Address Addr = Mem->toAsmAddress(Asm);
-  const Variable *VarReg = llvm::cast<Variable>(getSrc(2));
+  const auto VarReg = llvm::cast<Variable>(getSrc(2));
   assert(VarReg->hasReg());
   const RegX8632::GPRRegister Reg =
       RegX8632::getEncodedGPR(VarReg->getRegNum());
   if (Locked) {
     Asm->LockCmpxchg(Ty, Addr, Reg);
   } else {
     Asm->cmpxchg(Ty, Addr, Reg);
   }
   emitIASBytes(Func, Asm, StartPosition);
 }
@@ skipping 14 matching lines @@
     Str << "\tlock";
   }
   Str << "\tcmpxchg8b\t";
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Cmpxchg8b::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 5);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
-  const OperandX8632Mem *Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
+  const auto Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
   assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   const x86::Address Addr = Mem->toAsmAddress(Asm);
   if (Locked) {
     Asm->lock();
   }
   Asm->cmpxchg8b(Addr);
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632Cmpxchg8b::dump(const Cfg *Func) const {
@@ skipping 131 matching lines @@
   getSrc(1)->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Ucomiss::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   // Currently src0 is always a variable by convention, to avoid having
   // two memory operands.
   assert(llvm::isa<Variable>(getSrc(0)));
-  const Variable *Src0 = llvm::cast<Variable>(getSrc(0));
-  Type Ty = Src0->getType();
+  const auto Src0Var = llvm::cast<Variable>(getSrc(0));
+  Type Ty = Src0Var->getType();
   const static x86::AssemblerX86::XmmEmitterRegOp Emitter = {
     &x86::AssemblerX86::ucomiss, &x86::AssemblerX86::ucomiss
   };
-  emitIASRegOpTyXMM(Func, Ty, Src0, getSrc(1), Emitter);
+  emitIASRegOpTyXMM(Func, Ty, Src0Var, getSrc(1), Emitter);
 }
 
 void InstX8632Ucomiss::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "ucomiss." << getSrc(0)->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632UD2::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
@@ skipping 22 matching lines @@
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Test::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Src0 = getSrc(0);
   const Operand *Src1 = getSrc(1);
   Type Ty = Src0->getType();
   // The Reg/Addr form of test is not encodeable.
   static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = {
-    &x86::AssemblerX86::test, NULL, &x86::AssemblerX86::test
-  };
+      &x86::AssemblerX86::test, nullptr, &x86::AssemblerX86::test};
   static const x86::AssemblerX86::GPREmitterAddrOp AddrEmitter = {
     &x86::AssemblerX86::test, &x86::AssemblerX86::test
   };
   if (const auto SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
     if (SrcVar0->hasReg()) {
       emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
       return;
     }
   }
   llvm_unreachable("Nothing actually generates this so it's untested");
@@ skipping 35 matching lines @@
   getSrc(1)->emit(Func);
 }
 
 void InstX8632Store::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Dest = getSrc(1);
   const Operand *Src = getSrc(0);
   Type DestTy = Dest->getType();
   if (isScalarFloatingType(DestTy)) {
     // Src must be a register, since Dest is a Mem operand of some kind.
-    const Variable *SrcVar = llvm::cast<Variable>(Src);
+    const auto SrcVar = llvm::cast<Variable>(Src);
     assert(SrcVar->hasReg());
     RegX8632::XmmRegister SrcReg = RegX8632::getEncodedXmm(SrcVar->getRegNum());
     x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
     intptr_t StartPosition = Asm->GetPosition();
     if (const auto DestVar = llvm::dyn_cast<Variable>(Dest)) {
       assert(!DestVar->hasReg());
       x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget())
                                  ->stackVarToAsmOperand(DestVar));
       Asm->movss(DestTy, StackAddr, SrcReg);
     } else {
@@ skipping 25 matching lines @@
   Str << "\tmovups\t";
   getSrc(0)->emit(Func);
   Str << ", ";
   getSrc(1)->emit(Func);
 }
 
 void InstX8632StoreP::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 2);
-  const Variable *Src = llvm::cast<Variable>(getSrc(0));
-  const OperandX8632Mem *DestMem = llvm::cast<OperandX8632Mem>(getSrc(1));
+  const auto SrcVar = llvm::cast<Variable>(getSrc(0));
+  const auto DestMem = llvm::cast<OperandX8632Mem>(getSrc(1));
   assert(DestMem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
-  assert(Src->hasReg());
+  assert(SrcVar->hasReg());
   Asm->movups(DestMem->toAsmAddress(Asm),
-              RegX8632::getEncodedXmm(Src->getRegNum()));
+              RegX8632::getEncodedXmm(SrcVar->getRegNum()));
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632StoreP::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storep." << getSrc(0)->getType() << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
 void InstX8632StoreQ::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   assert(getSrc(1)->getType() == IceType_i64 ||
          getSrc(1)->getType() == IceType_f64);
   Str << "\tmovq\t";
   getSrc(0)->emit(Func);
   Str << ", ";
   getSrc(1)->emit(Func);
 }
 
 void InstX8632StoreQ::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 2);
-  const Variable *Src = llvm::cast<Variable>(getSrc(0));
-  const OperandX8632Mem *DestMem = llvm::cast<OperandX8632Mem>(getSrc(1));
+  const auto SrcVar = llvm::cast<Variable>(getSrc(0));
+  const auto DestMem = llvm::cast<OperandX8632Mem>(getSrc(1));
   assert(DestMem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
-  assert(Src->hasReg());
+  assert(SrcVar->hasReg());
   Asm->movq(DestMem->toAsmAddress(Asm),
-            RegX8632::getEncodedXmm(Src->getRegNum()));
+            RegX8632::getEncodedXmm(SrcVar->getRegNum()));
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632StoreQ::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storeq." << getSrc(0)->getType() << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
 template <> void InstX8632Lea::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
   Str << "\tleal\t";
   Operand *Src0 = getSrc(0);
-  if (Variable *VSrc0 = llvm::dyn_cast<Variable>(Src0)) {
-    Type Ty = VSrc0->getType();
+  if (const auto Src0Var = llvm::dyn_cast<Variable>(Src0)) {
+    Type Ty = Src0Var->getType();
     // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
     // acceptable type.
-    VSrc0->asType(isVectorType(Ty) ? IceType_i32 : Ty).emit(Func);
+    Src0Var->asType(isVectorType(Ty) ? IceType_i32 : Ty).emit(Func);
   } else {
     Src0->emit(Func);
   }
   Str << ", ";
   getDest()->emit(Func);
 }
 
 template <> void InstX8632Mov::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
@@ skipping 66 matching lines @@
       emitIASRegOpTyGPR(Func, DestTy, Dest, Src, GPRRegEmitter);
       return;
     }
   } else {
     // Dest must be Stack and Src *could* be a register. Use Src's type
     // to decide on the emitters.
     x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget())
                                ->stackVarToAsmOperand(Dest));
     if (isScalarFloatingType(SrcTy)) {
       // Src must be a register.
-      const Variable *SrcVar = llvm::cast<Variable>(Src);
+      const auto SrcVar = llvm::cast<Variable>(Src);
       assert(SrcVar->hasReg());
       x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
       intptr_t StartPosition = Asm->GetPosition();
       Asm->movss(SrcTy, StackAddr,
                  RegX8632::getEncodedXmm(SrcVar->getRegNum()));
       emitIASBytes(Func, Asm, StartPosition);
       return;
     } else {
       // Src can be a register or immediate.
       assert(isScalarIntegerType(SrcTy));
       emitIASAddrOpTyGPR(Func, SrcTy, StackAddr, Src, GPRAddrEmitter);
       return;
     }
     return;
   }
 }
 
 template <> void InstX8632Movd::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 1);
   const Variable *Dest = getDest();
-  const Variable *Src = llvm::cast<Variable>(getSrc(0));
+  const auto SrcVar = llvm::cast<Variable>(getSrc(0));
   // For insert/extract element (one of Src/Dest is an Xmm vector and
   // the other is an int type).
-  if (Src->getType() == IceType_i32) {
+  if (SrcVar->getType() == IceType_i32) {
     assert(isVectorType(Dest->getType()));
     assert(Dest->hasReg());
     RegX8632::XmmRegister DestReg = RegX8632::getEncodedXmm(Dest->getRegNum());
-    if (Src->hasReg()) {
-      Asm->movd(DestReg, RegX8632::getEncodedGPR(Src->getRegNum()));
+    if (SrcVar->hasReg()) {
+      Asm->movd(DestReg, RegX8632::getEncodedGPR(SrcVar->getRegNum()));
     } else {
       x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget())
-                                 ->stackVarToAsmOperand(Src));
+                                 ->stackVarToAsmOperand(SrcVar));
       Asm->movd(DestReg, StackAddr);
     }
   } else {
-    assert(isVectorType(Src->getType()));
-    assert(Src->hasReg());
+    assert(isVectorType(SrcVar->getType()));
+    assert(SrcVar->hasReg());
     assert(Dest->getType() == IceType_i32);
-    RegX8632::XmmRegister SrcReg = RegX8632::getEncodedXmm(Src->getRegNum());
+    RegX8632::XmmRegister SrcReg = RegX8632::getEncodedXmm(SrcVar->getRegNum());
     if (Dest->hasReg()) {
       Asm->movd(RegX8632::getEncodedGPR(Dest->getRegNum()), SrcReg);
     } else {
       x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget())
                                  ->stackVarToAsmOperand(Dest));
       Asm->movd(StackAddr, SrcReg);
     }
   }
   emitIASBytes(Func, Asm, StartPosition);
 }
@@ skipping 45 matching lines @@
   };
   emitIASMovlikeXMM(Func, Dest, Src, Emitter);
 }
 
 template <> void InstX8632MovssRegs::emitIAS(const Cfg *Func) const {
   // This is Binop variant is only intended to be used for reg-reg moves
   // where part of the Dest register is untouched.
   assert(getSrcSize() == 2);
   const Variable *Dest = getDest();
   assert(Dest == getSrc(0));
-  const Variable *Src = llvm::cast<Variable>(getSrc(1));
-  assert(Dest->hasReg() && Src->hasReg());
+  const auto SrcVar = llvm::cast<Variable>(getSrc(1));
+  assert(Dest->hasReg() && SrcVar->hasReg());
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Asm->movss(IceType_f32, RegX8632::getEncodedXmm(Dest->getRegNum()),
-             RegX8632::getEncodedXmm(Src->getRegNum()));
+             RegX8632::getEncodedXmm(SrcVar->getRegNum()));
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 template <> void InstX8632Movsx::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   // Dest must be a > 8-bit register, but Src can be 8-bit. In practice
   // we just use the full register for Dest to avoid having an
   // OperandSizeOverride prefix. It also allows us to only dispatch on SrcTy.
@@ skipping 30 matching lines @@
 void InstX8632Nop::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "nop (variant = " << Variant << ")";
 }
 
 void InstX8632Fld::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Type Ty = getSrc(0)->getType();
   SizeT Width = typeWidthInBytes(Ty);
-  Variable *Var = llvm::dyn_cast<Variable>(getSrc(0));
+  const auto Var = llvm::dyn_cast<Variable>(getSrc(0));
   if (Var && Var->hasReg()) {
     // This is a physical xmm register, so we need to spill it to a
     // temporary stack slot.
     Str << "\tsubl\t$" << Width << ", %esp"
         << "\n";
     Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t";
     Var->emit(Func);
     Str << ", (%esp)\n";
     Str << "\tfld" << getFldString(Ty) << "\t"
         << "(%esp)\n";
@@ skipping 38 matching lines @@
 
 void InstX8632Fld::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "fld." << getSrc(0)->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632Fstp::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 0);
-  // TODO(jvoung,stichnot): Utilize this by setting Dest to NULL to
+  // TODO(jvoung,stichnot): Utilize this by setting Dest to nullptr to
   // "partially" delete the fstp if the Dest is unused.
   // Even if Dest is unused, the fstp should be kept for the SideEffects
   // of popping the stack.
-  if (getDest() == NULL) {
+  if (!getDest()) {
     Str << "\tfstp\tst(0)";
     return;
   }
   Type Ty = getDest()->getType();
   size_t Width = typeWidthInBytes(Ty);
   if (!getDest()->hasReg()) {
     Str << "\tfstp" << getFldString(Ty) << "\t";
     getDest()->emit(Func);
     return;
   }
   // Dest is a physical (xmm) register, so st(0) needs to go through
   // memory.  Hack this by creating a temporary stack slot, spilling
   // st(0) there, loading it into the xmm register, and deallocating
   // the stack slot.
   Str << "\tsubl\t$" << Width << ", %esp\n";
   Str << "\tfstp" << getFldString(Ty) << "\t"
       << "(%esp)\n";
   Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t"
       << "(%esp), ";
   getDest()->emit(Func);
   Str << "\n";
   Str << "\taddl\t$" << Width << ", %esp";
 }
 
 void InstX8632Fstp::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 0);
   const Variable *Dest = getDest();
-  // TODO(jvoung,stichnot): Utilize this by setting Dest to NULL to
+  // TODO(jvoung,stichnot): Utilize this by setting Dest to nullptr to
   // "partially" delete the fstp if the Dest is unused.
   // Even if Dest is unused, the fstp should be kept for the SideEffects
   // of popping the stack.
-  if (Dest == NULL) {
+  if (!Dest) {
     Asm->fstp(RegX8632::getEncodedSTReg(0));
     emitIASBytes(Func, Asm, StartPosition);
     return;
   }
   Type Ty = Dest->getType();
   if (!Dest->hasReg()) {
     x86::Address StackAddr(static_cast<TargetX8632 *>(Func->getTarget())
                                ->stackVarToAsmOperand(Dest));
     Asm->fstp(Ty, StackAddr);
   } else {
@@ skipping 63 matching lines @@
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
              TargetX8632::SSE4_1);
   // pextrw must take a register dest. There is an SSE4.1 version that takes
   // a memory dest, but we aren't using it. For uniformity, just restrict
   // them all to have a register dest for now.
   assert(Dest->hasReg());
   // pextrw's Src(0) must be a register (both SSE4.1 and SSE2).
   assert(llvm::cast<Variable>(getSrc(0))->hasReg());
   static const x86::AssemblerX86::ThreeOpImmEmitter<
       RegX8632::GPRRegister, RegX8632::XmmRegister> Emitter = {
-      &x86::AssemblerX86::pextr, NULL};
+      &x86::AssemblerX86::pextr, nullptr};
   emitIASThreeOpImmOps<RegX8632::GPRRegister, RegX8632::XmmRegister,
                        RegX8632::getEncodedGPR, RegX8632::getEncodedXmm>(
       Func, DispatchTy, Dest, getSrc(0), getSrc(1), Emitter);
 }
 
 template <> void InstX8632Pinsr::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
   // pinsrb and pinsrd are SSE4.1 instructions.
   assert(getDest()->getType() == IceType_v8i16 ||
          getDest()->getType() == IceType_v8i1 ||
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
              >= TargetX8632::SSE4_1);
   Str << "\t" << Opcode
       << TypeX8632Attributes[getDest()->getType()].PackString << "\t";
   getSrc(2)->emit(Func);
   Str << ", ";
   Operand *Src1 = getSrc(1);
-  if (Variable *VSrc1 = llvm::dyn_cast<Variable>(Src1)) {
+  if (const auto Src1Var = llvm::dyn_cast<Variable>(Src1)) {
     // If src1 is a register, it should always be r32.
-    if (VSrc1->hasReg()) {
-      VSrc1->asType(IceType_i32).emit(Func);
+    if (Src1Var->hasReg()) {
+      Src1Var->asType(IceType_i32).emit(Func);
     } else {
-      VSrc1->emit(Func);
+      Src1Var->emit(Func);
     }
   } else {
     Src1->emit(Func);
   }
   Str << ", ";
   getDest()->emit(Func);
 }
 
 template <> void InstX8632Pinsr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
@@ skipping 83 matching lines @@
 
 void InstX8632AdjustStack::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "esp = sub.i32 esp, " << Amount;
 }
 
 void InstX8632Push::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   // Push is currently only used for saving GPRs.
-  Variable *Var = llvm::cast<Variable>(getSrc(0));
+  const auto Var = llvm::cast<Variable>(getSrc(0));
   assert(Var->hasReg());
   Str << "\tpush\t";
   Var->emit(Func);
 }
 
 void InstX8632Push::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   // Push is currently only used for saving GPRs.
-  Variable *Var = llvm::cast<Variable>(getSrc(0));
+  const auto Var = llvm::cast<Variable>(getSrc(0));
   assert(Var->hasReg());
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Asm->pushl(RegX8632::getEncodedGPR(Var->getRegNum()));
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632Push::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "push." << getSrc(0)->getType() << " ";
@@ skipping 50 matching lines @@
   getSrc(1)->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Xadd::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Type Ty = getSrc(0)->getType();
-  const OperandX8632Mem *Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
+  const auto Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
   assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   const x86::Address Addr = Mem->toAsmAddress(Asm);
-  const Variable *VarReg = llvm::cast<Variable>(getSrc(1));
+  const auto VarReg = llvm::cast<Variable>(getSrc(1));
   assert(VarReg->hasReg());
   const RegX8632::GPRRegister Reg =
       RegX8632::getEncodedGPR(VarReg->getRegNum());
   if (Locked) {
     Asm->lock();
   }
   Asm->xadd(Ty, Addr, Reg);
   emitIASBytes(Func, Asm, StartPosition);
 }
 
@@ skipping 13 matching lines @@
   getSrc(1)->emit(Func);
   Str << ", ";
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Xchg::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Type Ty = getSrc(0)->getType();
-  const OperandX8632Mem *Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
+  const auto Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
   assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   const x86::Address Addr = Mem->toAsmAddress(Asm);
-  const Variable *VarReg = llvm::cast<Variable>(getSrc(1));
+  const auto VarReg = llvm::cast<Variable>(getSrc(1));
   assert(VarReg->hasReg());
   const RegX8632::GPRRegister Reg =
       RegX8632::getEncodedGPR(VarReg->getRegNum());
   Asm->xchg(Ty, Addr, Reg);
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632Xchg::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Type Ty = getSrc(0)->getType();
   Str << "xchg." << Ty << " ";
   dumpSources(Func);
 }
 
 void OperandX8632Mem::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Str << InstX8632SegmentRegNames[SegmentReg] << ":";
   }
   // Emit as Offset(Base,Index,1<<Shift).
   // Offset is emitted without the leading '$'.
-  // Omit the (Base,Index,1<<Shift) part if Base==NULL.
-  if (Offset == NULL) {
+  // Omit the (Base,Index,1<<Shift) part if Base==nullptr.
+  if (!Offset) {
     // No offset, emit nothing.
-  } else if (auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
     if (CI->getValue())
       // Emit a non-zero offset without a leading '$'.
       Str << CI->getValue();
-  } else if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
+  } else if (const auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
     CR->emitWithoutDollar(Func->getContext());
   } else {
     llvm_unreachable("Invalid offset type for x86 mem operand");
   }
 
   if (Base) {
     Str << "(";
     Base->emit(Func);
     if (Index) {
       Str << ",";
@@ skipping 26 matching lines @@
       Str << (1u << Shift) << "*";
     if (Func)
       Index->dump(Func);
     else
       Index->dump(Str);
     Dumped = true;
   }
   // Pretty-print the Offset.
   bool OffsetIsZero = false;
   bool OffsetIsNegative = false;
-  if (Offset == NULL) {
+  if (!Offset) {
     OffsetIsZero = true;
-  } else if (ConstantInteger32 *CI =
-                 llvm::dyn_cast<ConstantInteger32>(Offset)) {
+  } else if (const auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
     OffsetIsZero = (CI->getValue() == 0);
     OffsetIsNegative = (static_cast<int32_t>(CI->getValue()) < 0);
   } else {
     assert(llvm::isa<ConstantRelocatable>(Offset));
   }
   if (Dumped) {
     if (!OffsetIsZero) {     // Suppress if Offset is known to be 0
       if (!OffsetIsNegative) // Suppress if Offset is known to be negative
         Str << "+";
       Offset->dump(Func, Str);
     }
   } else {
     // There is only the offset.
     Offset->dump(Func, Str);
   }
   Str << "]";
 }
 
 void OperandX8632Mem::emitSegmentOverride(x86::AssemblerX86 *Asm) const {
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Asm->EmitSegmentOverride(InstX8632SegmentPrefixes[SegmentReg]);
   }
 }
 
 x86::Address OperandX8632Mem::toAsmAddress(Assembler *Asm) const {
   int32_t Disp = 0;
-  AssemblerFixup *Fixup = NULL;
+  AssemblerFixup *Fixup = nullptr;
   // Determine the offset (is it relocatable?)
   if (getOffset()) {
-    if (ConstantInteger32 *CI =
-            llvm::dyn_cast<ConstantInteger32>(getOffset())) {
+    if (const auto CI = llvm::dyn_cast<ConstantInteger32>(getOffset())) {
       Disp = static_cast<int32_t>(CI->getValue());
-    } else if (ConstantRelocatable *CR =
+    } else if (const auto CR =
                    llvm::dyn_cast<ConstantRelocatable>(getOffset())) {
       Fixup = x86::DisplacementRelocation::create(Asm, FK_Abs_4, CR);
     } else {
       llvm_unreachable("Unexpected offset type");
     }
   }
 
   // Now convert to the various possible forms.
   if (getBase() && getIndex()) {
     return x86::Address(RegX8632::getEncodedGPR(getBase()->getRegNum()),
@@ skipping 49 matching lines @@
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice