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Unified Diff: src/compiler/arm/instruction-selector-arm.cc

Issue 697663003: [turbofan] Also optimize unsigned division by constant. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Slight improvement Created 6 years, 1 month ago
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Index: src/compiler/arm/instruction-selector-arm.cc
diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
index 3f3aff4541b0380d06ac2b76a09b4044a106a26d..a071bbccf8422ff371018a68085d46fea377505d 100644
--- a/src/compiler/arm/instruction-selector-arm.cc
+++ b/src/compiler/arm/instruction-selector-arm.cc
@@ -86,6 +86,7 @@ class ArmOperandGenerator : public OperandGenerator {
case kArmMls:
case kArmSmmul:
case kArmSmmla:
+ case kArmUmull:
case kArmSdiv:
case kArmUdiv:
case kArmBfc:
@@ -658,6 +659,15 @@ void InstructionSelector::VisitInt32MulHigh(Node* node) {
}
+void InstructionSelector::VisitUint32MulHigh(Node* node) {
+ ArmOperandGenerator g(this);
+ InstructionOperand* outputs[] = {g.TempRegister(), g.DefineAsRegister(node)};
+ InstructionOperand* inputs[] = {g.UseRegister(node->InputAt(0)),
+ g.UseRegister(node->InputAt(1))};
+ Emit(kArmUmull, arraysize(outputs), outputs, arraysize(inputs), inputs);
+}
+
+
static void EmitDiv(InstructionSelector* selector, ArchOpcode div_opcode,
ArchOpcode f64i32_opcode, ArchOpcode i32f64_opcode,
InstructionOperand* result_operand,
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