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Issue 697663003: [turbofan] Also optimize unsigned division by constant. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Slight improvement Created 6 years, 1 month ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/v8.h" 5 #include "src/v8.h"
6 6
7 #if V8_TARGET_ARCH_X64 7 #if V8_TARGET_ARCH_X64
8 8
9 #include "src/base/bits.h" 9 #include "src/base/bits.h"
10 #include "src/macro-assembler.h" 10 #include "src/macro-assembler.h"
(...skipping 917 matching lines...) Expand 10 before | Expand all | Expand 10 after
928 928
929 929
930 void Assembler::emit_imul(Register src, int size) { 930 void Assembler::emit_imul(Register src, int size) {
931 EnsureSpace ensure_space(this); 931 EnsureSpace ensure_space(this);
932 emit_rex(src, size); 932 emit_rex(src, size);
933 emit(0xF7); 933 emit(0xF7);
934 emit_modrm(0x5, src); 934 emit_modrm(0x5, src);
935 } 935 }
936 936
937 937
938 void Assembler::emit_imul(const Operand& src, int size) {
939 EnsureSpace ensure_space(this);
940 emit_rex(src, size);
941 emit(0xF7);
942 emit_operand(0x5, src);
943 }
944
945
938 void Assembler::emit_imul(Register dst, Register src, int size) { 946 void Assembler::emit_imul(Register dst, Register src, int size) {
939 EnsureSpace ensure_space(this); 947 EnsureSpace ensure_space(this);
940 emit_rex(dst, src, size); 948 emit_rex(dst, src, size);
941 emit(0x0F); 949 emit(0x0F);
942 emit(0xAF); 950 emit(0xAF);
943 emit_modrm(dst, src); 951 emit_modrm(dst, src);
944 } 952 }
945 953
946 954
947 void Assembler::emit_imul(Register dst, const Operand& src, int size) { 955 void Assembler::emit_imul(Register dst, const Operand& src, int size) {
(...skipping 544 matching lines...) Expand 10 before | Expand all | Expand 10 after
1492 1500
1493 1501
1494 void Assembler::emit_repmovs(int size) { 1502 void Assembler::emit_repmovs(int size) {
1495 EnsureSpace ensure_space(this); 1503 EnsureSpace ensure_space(this);
1496 emit(0xF3); 1504 emit(0xF3);
1497 emit_rex(size); 1505 emit_rex(size);
1498 emit(0xA5); 1506 emit(0xA5);
1499 } 1507 }
1500 1508
1501 1509
1502 void Assembler::mul(Register src) { 1510 void Assembler::mull(Register src) {
1511 EnsureSpace ensure_space(this);
1512 emit_optional_rex_32(src);
1513 emit(0xF7);
1514 emit_modrm(0x4, src);
1515 }
1516
1517
1518 void Assembler::mull(const Operand& src) {
1519 EnsureSpace ensure_space(this);
1520 emit_optional_rex_32(src);
1521 emit(0xF7);
1522 emit_operand(0x4, src);
1523 }
1524
1525
1526 void Assembler::mulq(Register src) {
1503 EnsureSpace ensure_space(this); 1527 EnsureSpace ensure_space(this);
1504 emit_rex_64(src); 1528 emit_rex_64(src);
1505 emit(0xF7); 1529 emit(0xF7);
1506 emit_modrm(0x4, src); 1530 emit_modrm(0x4, src);
1507 } 1531 }
1508 1532
1509 1533
1510 void Assembler::emit_neg(Register dst, int size) { 1534 void Assembler::emit_neg(Register dst, int size) {
1511 EnsureSpace ensure_space(this); 1535 EnsureSpace ensure_space(this);
1512 emit_rex(dst, size); 1536 emit_rex(dst, size);
(...skipping 1624 matching lines...) Expand 10 before | Expand all | Expand 10 after
3137 3161
3138 3162
3139 bool RelocInfo::IsInConstantPool() { 3163 bool RelocInfo::IsInConstantPool() {
3140 return false; 3164 return false;
3141 } 3165 }
3142 3166
3143 3167
3144 } } // namespace v8::internal 3168 } } // namespace v8::internal
3145 3169
3146 #endif // V8_TARGET_ARCH_X64 3170 #endif // V8_TARGET_ARCH_X64
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