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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 697663003: [turbofan] Also optimize unsigned division by constant. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Slight improvement Created 6 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 19 matching lines...) Expand all
30 V(Arm64Orn32) \ 30 V(Arm64Orn32) \
31 V(Arm64Eor) \ 31 V(Arm64Eor) \
32 V(Arm64Eor32) \ 32 V(Arm64Eor32) \
33 V(Arm64Eon) \ 33 V(Arm64Eon) \
34 V(Arm64Eon32) \ 34 V(Arm64Eon32) \
35 V(Arm64Sub) \ 35 V(Arm64Sub) \
36 V(Arm64Sub32) \ 36 V(Arm64Sub32) \
37 V(Arm64Mul) \ 37 V(Arm64Mul) \
38 V(Arm64Mul32) \ 38 V(Arm64Mul32) \
39 V(Arm64Smull) \ 39 V(Arm64Smull) \
40 V(Arm64Umull) \
40 V(Arm64Madd) \ 41 V(Arm64Madd) \
41 V(Arm64Madd32) \ 42 V(Arm64Madd32) \
42 V(Arm64Msub) \ 43 V(Arm64Msub) \
43 V(Arm64Msub32) \ 44 V(Arm64Msub32) \
44 V(Arm64Mneg) \ 45 V(Arm64Mneg) \
45 V(Arm64Mneg32) \ 46 V(Arm64Mneg32) \
46 V(Arm64Idiv) \ 47 V(Arm64Idiv) \
47 V(Arm64Idiv32) \ 48 V(Arm64Idiv32) \
48 V(Arm64Udiv) \ 49 V(Arm64Udiv) \
49 V(Arm64Udiv32) \ 50 V(Arm64Udiv32) \
(...skipping 74 matching lines...) Expand 10 before | Expand all | Expand 10 after
124 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 125 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
125 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 126 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
126 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 127 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
127 V(Operand2_R_ROR_I) /* %r0 ROR K */ 128 V(Operand2_R_ROR_I) /* %r0 ROR K */
128 129
129 } // namespace internal 130 } // namespace internal
130 } // namespace compiler 131 } // namespace compiler
131 } // namespace v8 132 } // namespace v8
132 133
133 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 134 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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