OLD | NEW |
1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ | 5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ |
6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ | 6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ |
7 | 7 |
8 #include <ctype.h> | 8 #include <ctype.h> |
9 | 9 |
10 #include "src/globals.h" | 10 #include "src/globals.h" |
(...skipping 1108 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1119 | 1119 |
1120 void MacroAssembler::Smulh(const Register& rd, | 1120 void MacroAssembler::Smulh(const Register& rd, |
1121 const Register& rn, | 1121 const Register& rn, |
1122 const Register& rm) { | 1122 const Register& rm) { |
1123 DCHECK(allow_macro_instructions_); | 1123 DCHECK(allow_macro_instructions_); |
1124 DCHECK(!rd.IsZero()); | 1124 DCHECK(!rd.IsZero()); |
1125 smulh(rd, rn, rm); | 1125 smulh(rd, rn, rm); |
1126 } | 1126 } |
1127 | 1127 |
1128 | 1128 |
| 1129 void MacroAssembler::Umull(const Register& rd, const Register& rn, |
| 1130 const Register& rm) { |
| 1131 DCHECK(allow_macro_instructions_); |
| 1132 DCHECK(!rd.IsZero()); |
| 1133 umaddl(rd, rn, rm, xzr); |
| 1134 } |
| 1135 |
| 1136 |
1129 void MacroAssembler::Stnp(const CPURegister& rt, | 1137 void MacroAssembler::Stnp(const CPURegister& rt, |
1130 const CPURegister& rt2, | 1138 const CPURegister& rt2, |
1131 const MemOperand& dst) { | 1139 const MemOperand& dst) { |
1132 DCHECK(allow_macro_instructions_); | 1140 DCHECK(allow_macro_instructions_); |
1133 stnp(rt, rt2, dst); | 1141 stnp(rt, rt2, dst); |
1134 } | 1142 } |
1135 | 1143 |
1136 | 1144 |
1137 void MacroAssembler::Sxtb(const Register& rd, const Register& rn) { | 1145 void MacroAssembler::Sxtb(const Register& rd, const Register& rn) { |
1138 DCHECK(allow_macro_instructions_); | 1146 DCHECK(allow_macro_instructions_); |
(...skipping 560 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1699 // characters are reserved for controlling features of the instrumentation. | 1707 // characters are reserved for controlling features of the instrumentation. |
1700 DCHECK(isprint(marker_name[0]) && isprint(marker_name[1])); | 1708 DCHECK(isprint(marker_name[0]) && isprint(marker_name[1])); |
1701 | 1709 |
1702 InstructionAccurateScope scope(this, 1); | 1710 InstructionAccurateScope scope(this, 1); |
1703 movn(xzr, (marker_name[1] << 8) | marker_name[0]); | 1711 movn(xzr, (marker_name[1] << 8) | marker_name[0]); |
1704 } | 1712 } |
1705 | 1713 |
1706 } } // namespace v8::internal | 1714 } } // namespace v8::internal |
1707 | 1715 |
1708 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ | 1716 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_INL_H_ |
OLD | NEW |