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Side by Side Diff: src/compiler/arm64/instruction-codes-arm64.h

Issue 697653002: [turbofan] Select tbz/tbnz when possible on ARM64. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 5 #ifndef V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 6 #define V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 49 matching lines...) Expand 10 before | Expand all | Expand 10 after
60 V(Arm64Lsr) \ 60 V(Arm64Lsr) \
61 V(Arm64Lsr32) \ 61 V(Arm64Lsr32) \
62 V(Arm64Asr) \ 62 V(Arm64Asr) \
63 V(Arm64Asr32) \ 63 V(Arm64Asr32) \
64 V(Arm64Ror) \ 64 V(Arm64Ror) \
65 V(Arm64Ror32) \ 65 V(Arm64Ror32) \
66 V(Arm64Mov32) \ 66 V(Arm64Mov32) \
67 V(Arm64Sxtw) \ 67 V(Arm64Sxtw) \
68 V(Arm64Ubfx) \ 68 V(Arm64Ubfx) \
69 V(Arm64Ubfx32) \ 69 V(Arm64Ubfx32) \
70 V(Arm64Tbz) \
71 V(Arm64Tbz32) \
72 V(Arm64Tbnz) \
73 V(Arm64Tbnz32) \
70 V(Arm64Claim) \ 74 V(Arm64Claim) \
71 V(Arm64Poke) \ 75 V(Arm64Poke) \
72 V(Arm64PokePairZero) \ 76 V(Arm64PokePairZero) \
73 V(Arm64PokePair) \ 77 V(Arm64PokePair) \
74 V(Arm64Float64Cmp) \ 78 V(Arm64Float64Cmp) \
75 V(Arm64Float64Add) \ 79 V(Arm64Float64Add) \
76 V(Arm64Float64Sub) \ 80 V(Arm64Float64Sub) \
77 V(Arm64Float64Mul) \ 81 V(Arm64Float64Mul) \
78 V(Arm64Float64Div) \ 82 V(Arm64Float64Div) \
79 V(Arm64Float64Mod) \ 83 V(Arm64Float64Mod) \
(...skipping 44 matching lines...) Expand 10 before | Expand all | Expand 10 after
124 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 128 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
125 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 129 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
126 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 130 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
127 V(Operand2_R_ROR_I) /* %r0 ROR K */ 131 V(Operand2_R_ROR_I) /* %r0 ROR K */
128 132
129 } // namespace internal 133 } // namespace internal
130 } // namespace compiler 134 } // namespace compiler
131 } // namespace v8 135 } // namespace v8
132 136
133 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_ 137 #endif // V8_COMPILER_ARM64_INSTRUCTION_CODES_ARM64_H_
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