enable packed double precision 3 operand mem/simd register avx1 instructions.

src/trusted/validator_ragel/proof_tools_templates.py

Index: src/trusted/validator_ragel/proof_tools_templates.py
diff --git a/src/trusted/validator_ragel/proof_tools_templates.py b/src/trusted/validator_ragel/proof_tools_templates.py
index 939a78a14d0b54f00489079c52078546fd5a61f9..b43c2d8a18489e48dfe680a8f7d94ad922b5efd0 100644
--- a/src/trusted/validator_ragel/proof_tools_templates.py
+++ b/src/trusted/validator_ragel/proof_tools_templates.py
@@ -31,3 +31,27 @@ def LockedRegWithRegOrMem16bit(mnemonic_name, bitness):
   lock = proof_tools.LockPrefix()
   return (proof_tools.OpsProd(lock, instr, reg16, mem) |
           proof_tools.OpsProd(instr, reg16, reg16 | mem))
+
+
+def XmmYmmOrMemory3operand(mnemonic_name, bitness):
+  """Set of 3 operand xmm/ymm/memory ops (memory is a possible source operand).
+
+  e.g.
+
+  instr xmm1/mem, xmm2, xmm3
+  or
+  instr ymm1/mem, ymm2, ymm3
+
+  Args:
+    mnemonic_name: the mnemonic we are producing the pattern for.
+    bitness: the bitness of the architecture (32 or 64)
+  Returns:
+    All possible disassembly sequences that follow the pattern.
+  """
+  xmm = proof_tools.AllXMMOperands(bitness)
+  ymm = proof_tools.AllYMMOperands(bitness)
+  mem = proof_tools.AllMemoryOperands(bitness)
+  mnemonic = proof_tools.MnemonicOp(mnemonic_name)
+
+  return (proof_tools.OpsProd(mnemonic, (xmm | mem), xmm, xmm) |
+          proof_tools.OpsProd(mnemonic, (ymm | mem), ymm, ymm))