Subzero: Switch to AT&T asm syntax. I give up.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 34 matching lines @@
   { emit }                                                                     \
   ,
     ICEINSTX8632CMPPS_TABLE
 #undef X
   };
 
 const struct TypeX8632Attributes_ {
   const char *CvtString;   // i (integer), s (single FP), d (double FP)
   const char *SdSsString;  // ss, sd, or <blank>
   const char *PackString;  // b, w, d, or <blank>
-  const char *WidthString; // {byte,word,dword,qword} ptr
+  const char *WidthString; // b, w, l, q, or <blank>
+  const char *FldString;   // s, l, or <blank>
 } TypeX8632Attributes[] = {
-#define X(tag, elementty, cvt, sdss, pack, width)                              \
-  { cvt, "" sdss, pack, width }                                                \
+#define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
+  { cvt, sdss, pack, width, fld }                                              \
   ,
     ICETYPEX8632_TABLE
 #undef X
   };
 
 const char *InstX8632SegmentRegNames[] = {
 #define X(val, name, prefix) name,
     SEG_REGX8632_TABLE
 #undef X
 };
 
 uint8_t InstX8632SegmentPrefixes[] = {
 #define X(val, name, prefix) prefix,
     SEG_REGX8632_TABLE
 #undef X
 };
 
 } // end of anonymous namespace
 
 const char *InstX8632::getWidthString(Type Ty) {
   return TypeX8632Attributes[Ty].WidthString;
 }
 
+const char *InstX8632::getFldString(Type Ty) {
+  return TypeX8632Attributes[Ty].FldString;
+}
+
 OperandX8632Mem::OperandX8632Mem(Cfg *Func, Type Ty, Variable *Base,
                                  Constant *Offset, Variable *Index,
                                  uint16_t Shift, SegmentRegisters SegmentReg)
     : OperandX8632(kMem, Ty), Base(Base), Offset(Offset), Index(Index),
       Shift(Shift), SegmentReg(SegmentReg) {
   assert(Shift <= 3);
   Vars = NULL;
   NumVars = 0;
   if (Base)
     ++NumVars;
@@ skipping 429 matching lines @@
     if (getTargetFalse()) {
       Str << ", label %" << getTargetFalse()->getName();
     }
   }
 }
 
 void InstX8632Call::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\tcall\t";
-  getCallTarget()->emit(Func);
+  if (auto CallTarget = llvm::dyn_cast<ConstantRelocatable>(getCallTarget())) {
+    // TODO(stichnot): All constant targets should suppress the '$',
+    // not just relocatables.
+    CallTarget->emitWithoutDollar(Func->getContext());
+  } else {
+    Str << "*";
+    getCallTarget()->emit(Func);
+  }
   Func->getTarget()->resetStackAdjustment();
 }
 
 void InstX8632Call::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Operand *Target = getCallTarget();
   bool NeedsFallback = false;
   if (const auto Var = llvm::dyn_cast<Variable>(Target)) {
     if (Var->hasReg()) {
@@ skipping 48 matching lines @@
 }
 
 // The ShiftHack parameter is used to emit "cl" instead of "ecx" for
 // shift instructions, in order to be syntactically valid.  The
 // Opcode parameter needs to be char* and not IceString because of
 // template issues.
 void emitTwoAddress(const char *Opcode, const Inst *Inst, const Cfg *Func,
                     bool ShiftHack) {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
-  assert(Inst->getDest() == Inst->getSrc(0));
-  Str << "\t" << Opcode << "\t";
-  Inst->getDest()->emit(Func);
+  Variable *Dest = Inst->getDest();
+  assert(Dest == Inst->getSrc(0));
+  Operand *Src1 = Inst->getSrc(1);
+  Str << "\t" << Opcode << InstX8632::getWidthString(Dest->getType()) << "\t";
+  Variable *ShiftReg = llvm::dyn_cast<Variable>(Src1);
+  if (ShiftHack && ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx)
+    Str << "%cl";
+  else
+    Src1->emit(Func);
   Str << ", ";
-  bool EmittedSrc1 = false;
-  if (ShiftHack) {
-    Variable *ShiftReg = llvm::dyn_cast<Variable>(Inst->getSrc(1));
-    if (ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx) {
-      Str << "cl";
-      EmittedSrc1 = true;
-    }
-  }
-  if (!EmittedSrc1)
-    Inst->getSrc(1)->emit(Func);
+  Dest->emit(Func);
 }
 
 void emitIASOpTyGPR(const Cfg *Func, Type Ty, const Operand *Op,
                     const x86::AssemblerX86::GPREmitterOneOp &Emitter) {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   if (const auto Var = llvm::dyn_cast<Variable>(Op)) {
     if (Var->hasReg()) {
       // We cheat a little and use GPRRegister even for byte operations.
       RegX8632::GPRRegister VarReg =
@@ skipping 311 matching lines @@
 }
 
 // In-place ops
 template <> const char *InstX8632Bswap::Opcode = "bswap";
 template <> const char *InstX8632Neg::Opcode = "neg";
 // Unary ops
 template <> const char *InstX8632Bsf::Opcode = "bsf";
 template <> const char *InstX8632Bsr::Opcode = "bsr";
 template <> const char *InstX8632Lea::Opcode = "lea";
 template <> const char *InstX8632Movd::Opcode = "movd";
-template <> const char *InstX8632Movsx::Opcode = "movsx";
-template <> const char *InstX8632Movzx::Opcode = "movzx";
+template <> const char *InstX8632Movsx::Opcode = "movs";
+template <> const char *InstX8632Movzx::Opcode = "movz";
 template <> const char *InstX8632Sqrtss::Opcode = "sqrtss";
 template <> const char *InstX8632Cbwdq::Opcode = "cbw/cwd/cdq";
 // Mov-like ops
 template <> const char *InstX8632Mov::Opcode = "mov";
 template <> const char *InstX8632Movp::Opcode = "movups";
 template <> const char *InstX8632Movq::Opcode = "movq";
 // Binary ops
 template <> const char *InstX8632Add::Opcode = "add";
 template <> const char *InstX8632Addps::Opcode = "addps";
 template <> const char *InstX8632Adc::Opcode = "adc";
@@ skipping 190 matching lines @@
 const x86::AssemblerX86::XmmEmitterShiftOp InstX8632Psra::Emitter = {
     &x86::AssemblerX86::psra, &x86::AssemblerX86::psra,
     &x86::AssemblerX86::psra};
 
 template <> void InstX8632Sqrtss::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Type Ty = getSrc(0)->getType();
   assert(isScalarFloatingType(Ty));
   Str << "\tsqrt" << TypeX8632Attributes[Ty].SdSsString << "\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   getDest()->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
 }
 
 template <> void InstX8632Addss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "add%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Padd::emit(const Cfg *Func) const {
@@ skipping 66 matching lines @@
 template <> void InstX8632Divss::emit(const Cfg *Func) const {
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "div%s",
            TypeX8632Attributes[getDest()->getType()].SdSsString);
   emitTwoAddress(buf, this, Func);
 }
 
 template <> void InstX8632Div::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
-  Str << "\t" << Opcode << "\t";
-  getSrc(1)->emit(Func);
+  Operand *Src1 = getSrc(1);
+  Str << "\t" << Opcode << getWidthString(Src1->getType()) << "\t";
+  Src1->emit(Func);
 }
 
 template <> void InstX8632Div::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   const Operand *Src = getSrc(1);
   Type Ty = Src->getType();
   const static x86::AssemblerX86::GPREmitterOneOp Emitter = {
       &x86::AssemblerX86::div, &x86::AssemblerX86::div};
   emitIASOpTyGPR(Func, Ty, Src, Emitter);
 }
 
 template <> void InstX8632Idiv::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
-  Str << "\t" << Opcode << "\t";
-  getSrc(1)->emit(Func);
+  Operand *Src1 = getSrc(1);
+  Str << "\t" << Opcode << getWidthString(Src1->getType()) << "\t";
+  Src1->emit(Func);
 }
 
 template <> void InstX8632Idiv::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   const Operand *Src = getSrc(1);
   Type Ty = Src->getType();
   const static x86::AssemblerX86::GPREmitterOneOp Emitter = {
       &x86::AssemblerX86::idiv, &x86::AssemblerX86::idiv};
   emitIASOpTyGPR(Func, Ty, Src, Emitter);
 }
 
 namespace {
 
 // pblendvb and blendvps take xmm0 as a final implicit argument.
 void emitVariableBlendInst(const char *Opcode, const Inst *Inst,
                            const Cfg *Func) {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 3);
   assert(llvm::cast<Variable>(Inst->getSrc(2))->getRegNum() ==
          RegX8632::Reg_xmm0);
   Str << "\t" << Opcode << "\t";
+  Inst->getSrc(1)->emit(Func);
+  Str << ", ";
   Inst->getDest()->emit(Func);
-  Str << ", ";
-  Inst->getSrc(1)->emit(Func);
 }
 
 void
 emitIASVariableBlendInst(const Inst *Inst, const Cfg *Func,
                          const x86::AssemblerX86::XmmEmitterRegOp &Emitter) {
   assert(Inst->getSrcSize() == 3);
   assert(llvm::cast<Variable>(Inst->getSrc(2))->getRegNum() ==
          RegX8632::Reg_xmm0);
   const Variable *Dest = Inst->getDest();
   const Operand *Src = Inst->getSrc(1);
@@ skipping 26 matching lines @@
   assert(static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
          TargetX8632::SSE4_1);
   static const x86::AssemblerX86::XmmEmitterRegOp Emitter = {
       &x86::AssemblerX86::pblendvb, &x86::AssemblerX86::pblendvb};
   emitIASVariableBlendInst(this, Func, Emitter);
 }
 
 template <> void InstX8632Imul::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
-  if (isByteSizedArithType(getDest()->getType())) {
+  Variable *Dest = getDest();
+  if (isByteSizedArithType(Dest->getType())) {
     // The 8-bit version of imul only allows the form "imul r/m8".
     Variable *Src0 = llvm::dyn_cast<Variable>(getSrc(0));
     (void)Src0;
     assert(Src0 && Src0->getRegNum() == RegX8632::Reg_eax);
-    Str << "\timul\t";
+    Str << "\timulb\t";
     getSrc(1)->emit(Func);
   } else if (llvm::isa<Constant>(getSrc(1))) {
-    Str << "\timul\t";
-    getDest()->emit(Func);
+    Str << "\timul" << getWidthString(Dest->getType()) << "\t";
+    getSrc(1)->emit(Func);
     Str << ", ";
     getSrc(0)->emit(Func);
     Str << ", ";
-    getSrc(1)->emit(Func);
+    Dest->emit(Func);
   } else {
     emitTwoAddress("imul", this, Func);
   }
 }
 
 template <> void InstX8632Imul::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Variable *Var = getDest();
   Type Ty = Var->getType();
   const Operand *Src = getSrc(1);
@@ skipping 36 matching lines @@
   assert(getSrcSize() == 1);
   Operand *Src0 = getSrc(0);
   assert(llvm::isa<Variable>(Src0));
   assert(llvm::cast<Variable>(Src0)->getRegNum() == RegX8632::Reg_eax);
   switch (Src0->getType()) {
   default:
     llvm_unreachable("unexpected source type!");
     break;
   case IceType_i8:
     assert(getDest()->getRegNum() == RegX8632::Reg_eax);
-    Str << "\tcbw";
+    Str << "\tcbtw";
     break;
   case IceType_i16:
     assert(getDest()->getRegNum() == RegX8632::Reg_edx);
-    Str << "\tcwd";
+    Str << "\tcwtd";
     break;
   case IceType_i32:
     assert(getDest()->getRegNum() == RegX8632::Reg_edx);
-    Str << "\tcdq";
+    Str << "\tcltd";
     break;
   }
 }
 
 template <> void InstX8632Cbwdq::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 1);
   Operand *Src0 = getSrc(0);
   assert(llvm::isa<Variable>(Src0));
@@ skipping 17 matching lines @@
   }
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632Mul::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   assert(llvm::isa<Variable>(getSrc(0)));
   assert(llvm::dyn_cast<Variable>(getSrc(0))->getRegNum() == RegX8632::Reg_eax);
   assert(getDest()->getRegNum() == RegX8632::Reg_eax); // TODO: allow edx?
-  Str << "\tmul\t";
+  Str << "\tmul" << getWidthString(getDest()->getType()) << "\t";
   getSrc(1)->emit(Func);
 }
 
 void InstX8632Mul::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   assert(llvm::isa<Variable>(getSrc(0)));
   assert(llvm::dyn_cast<Variable>(getSrc(0))->getRegNum() == RegX8632::Reg_eax);
   assert(getDest()->getRegNum() == RegX8632::Reg_eax); // TODO: allow edx?
   const Operand *Src = getSrc(1);
   Type Ty = Src->getType();
   const static x86::AssemblerX86::GPREmitterOneOp Emitter = {
       &x86::AssemblerX86::mul, &x86::AssemblerX86::mul};
   emitIASOpTyGPR(Func, Ty, Src, Emitter);
 }
 
 void InstX8632Mul::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = mul." << getDest()->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632Shld::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
+  Variable *Dest = getDest();
   assert(getSrcSize() == 3);
-  assert(getDest() == getSrc(0));
-  Str << "\tshld\t";
-  getDest()->emit(Func);
+  assert(Dest == getSrc(0));
+  Str << "\tshld" << getWidthString(Dest->getType()) << "\t";
+  if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+    (void)ShiftReg;
+    assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
+    Str << "%cl";
+  } else {
+    getSrc(2)->emit(Func);
+  }
   Str << ", ";
   getSrc(1)->emit(Func);
   Str << ", ";
-  if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
-    (void)ShiftReg;
-    assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
-    Str << "cl";
-  } else {
-    getSrc(2)->emit(Func);
-  }
+  Dest->emit(Func);
 }
 
 void InstX8632Shld::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   assert(getDest() == getSrc(0));
   const Variable *Dest = getDest();
   const Operand *Src1 = getSrc(1);
   const Operand *Src2 = getSrc(2);
   static const x86::AssemblerX86::GPREmitterShiftD Emitter = {
       &x86::AssemblerX86::shld, &x86::AssemblerX86::shld};
   emitIASGPRShiftDouble(Func, Dest, Src1, Src2, Emitter);
 }
 
 void InstX8632Shld::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = shld." << getDest()->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632Shrd::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
+  Variable *Dest = getDest();
   assert(getSrcSize() == 3);
-  assert(getDest() == getSrc(0));
-  Str << "\tshrd\t";
-  getDest()->emit(Func);
+  assert(Dest == getSrc(0));
+  Str << "\tshrd" << getWidthString(Dest->getType()) << "\t";
+  if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
+    (void)ShiftReg;
+    assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
+    Str << "%cl";
+  } else {
+    getSrc(2)->emit(Func);
+  }
   Str << ", ";
   getSrc(1)->emit(Func);
   Str << ", ";
-  if (Variable *ShiftReg = llvm::dyn_cast<Variable>(getSrc(2))) {
-    (void)ShiftReg;
-    assert(ShiftReg->getRegNum() == RegX8632::Reg_ecx);
-    Str << "cl";
-  } else {
-    getSrc(2)->emit(Func);
-  }
+  Dest->emit(Func);
 }
 
 void InstX8632Shrd::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   assert(getDest() == getSrc(0));
   const Variable *Dest = getDest();
   const Operand *Src1 = getSrc(1);
   const Operand *Src2 = getSrc(2);
   static const x86::AssemblerX86::GPREmitterShiftD Emitter = {
       &x86::AssemblerX86::shrd, &x86::AssemblerX86::shrd};
   emitIASGPRShiftDouble(Func, Dest, Src1, Src2, Emitter);
 }
 
 void InstX8632Shrd::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = shrd." << getDest()->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632Cmov::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
+  Variable *Dest = getDest();
   Str << "\t";
   assert(Condition != CondX86::Br_None);
   assert(getDest()->hasReg());
-  Str << "cmov" << InstX8632BrAttributes[Condition].DisplayString << "\t";
-  getDest()->emit(Func);
+  Str << "cmov" << InstX8632BrAttributes[Condition].DisplayString
+      << getWidthString(Dest->getType()) << "\t";
+  getSrc(1)->emit(Func);
   Str << ", ";
-  getSrc(1)->emit(Func);
+  Dest->emit(Func);
 }
 
 void InstX8632Cmov::emitIAS(const Cfg *Func) const {
   assert(Condition != CondX86::Br_None);
   assert(getDest()->hasReg());
   assert(getSrcSize() == 2);
   // Only need the reg/reg form now.
   const Variable *Src = llvm::cast<Variable>(getSrc(1));
   assert(Src->hasReg());
   assert(Src->getType() == IceType_i32);
@@ skipping 13 matching lines @@
   dumpSources(Func);
 }
 
 void InstX8632Cmpps::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   assert(Condition < CondX86::Cmpps_Invalid);
   Str << "\t";
   Str << "cmp" << InstX8632CmppsAttributes[Condition].EmitString << "ps"
       << "\t";
+  getSrc(1)->emit(Func);
+  Str << ", ";
   getDest()->emit(Func);
-  Str << ", ";
-  getSrc(1)->emit(Func);
 }
 
 void InstX8632Cmpps::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 2);
   assert(Condition < CondX86::Cmpps_Invalid);
   // Assuming there isn't any load folding for cmpps, and vector constants
   // are not allowed in PNaCl.
   assert(llvm::isa<Variable>(getSrc(1)));
@@ skipping 18 matching lines @@
       << "\t";
   dumpSources(Func);
 }
 
 void InstX8632Cmpxchg::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
   if (Locked) {
     Str << "\tlock";
   }
-  Str << "\tcmpxchg\t";
+  Str << "\tcmpxchg" << getWidthString(getSrc(0)->getType()) << "\t";
+  getSrc(2)->emit(Func);
+  Str << ", ";
   getSrc(0)->emit(Func);
-  Str << ", ";
-  getSrc(2)->emit(Func);
 }
 
 void InstX8632Cmpxchg::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Type Ty = getSrc(0)->getType();
   const OperandX8632Mem *Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
   assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   const x86::Address Addr = Mem->toAsmAddress(Asm);
@@ skipping 52 matching lines @@
 }
 
 void InstX8632Cvt::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\tcvt";
   if (isTruncating())
     Str << "t";
   Str << TypeX8632Attributes[getSrc(0)->getType()].CvtString << "2"
       << TypeX8632Attributes[getDest()->getType()].CvtString << "\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   getDest()->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
 }
 
 void InstX8632Cvt::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   Type DestTy = Dest->getType();
   Type SrcTy = Src->getType();
   switch (Variant) {
   case Si2ss: {
@@ skipping 55 matching lines @@
   if (isTruncating())
     Str << "t";
   Str << TypeX8632Attributes[getSrc(0)->getType()].CvtString << "2"
       << TypeX8632Attributes[getDest()->getType()].CvtString << " ";
   dumpSources(Func);
 }
 
 void InstX8632Icmp::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
-  Str << "\tcmp\t";
+  Str << "\tcmp" << getWidthString(getSrc(0)->getType()) << "\t";
+  getSrc(1)->emit(Func);
+  Str << ", ";
   getSrc(0)->emit(Func);
-  Str << ", ";
-  getSrc(1)->emit(Func);
 }
 
 void InstX8632Icmp::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Src0 = getSrc(0);
   const Operand *Src1 = getSrc(1);
   Type Ty = Src0->getType();
   static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = {
     &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp, &x86::AssemblerX86::cmp
   };
@@ skipping 13 matching lines @@
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "cmp." << getSrc(0)->getType() << " ";
   dumpSources(Func);
 }
 
 void InstX8632Ucomiss::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   Str << "\tucomi" << TypeX8632Attributes[getSrc(0)->getType()].SdSsString
       << "\t";
+  getSrc(1)->emit(Func);
+  Str << ", ";
   getSrc(0)->emit(Func);
-  Str << ", ";
-  getSrc(1)->emit(Func);
 }
 
 void InstX8632Ucomiss::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   // Currently src0 is always a variable by convention, to avoid having
   // two memory operands.
   assert(llvm::isa<Variable>(getSrc(0)));
   const Variable *Src0 = llvm::cast<Variable>(getSrc(0));
   Type Ty = Src0->getType();
   const static x86::AssemblerX86::XmmEmitterRegOp Emitter = {
@@ skipping 22 matching lines @@
 }
 
 void InstX8632UD2::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "ud2\n";
 }
 
 void InstX8632Test::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
-  Str << "\ttest\t";
+  Str << "\ttest" << getWidthString(getSrc(0)->getType()) << "\t";
+  getSrc(1)->emit(Func);
+  Str << ", ";
   getSrc(0)->emit(Func);
-  Str << ", ";
-  getSrc(1)->emit(Func);
 }
 
 void InstX8632Test::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Src0 = getSrc(0);
   const Operand *Src1 = getSrc(1);
   Type Ty = Src0->getType();
   // The Reg/Addr form of test is not encodeable.
   static const x86::AssemblerX86::GPREmitterRegOp RegEmitter = {
     &x86::AssemblerX86::test, NULL, &x86::AssemblerX86::test
@@ skipping 31 matching lines @@
 }
 
 void InstX8632Mfence::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "mfence\n";
 }
 
 void InstX8632Store::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
-  Str << "\tmov" << TypeX8632Attributes[getSrc(0)->getType()].SdSsString
+  Type Ty = getSrc(0)->getType();
+  Str << "\tmov" << getWidthString(Ty) << TypeX8632Attributes[Ty].SdSsString
       << "\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   getSrc(1)->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
 }
 
 void InstX8632Store::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   const Operand *Dest = getSrc(1);
   const Operand *Src = getSrc(0);
   Type DestTy = Dest->getType();
   if (isScalarFloatingType(DestTy)) {
     // Src must be a register, since Dest is a Mem operand of some kind.
     const Variable *SrcVar = llvm::cast<Variable>(Src);
@@ skipping 26 matching lines @@
   Str << "mov." << getSrc(0)->getType() << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
 void InstX8632StoreP::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   Str << "\tmovups\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   getSrc(1)->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
 }
 
 void InstX8632StoreP::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 2);
   const Variable *Src = llvm::cast<Variable>(getSrc(0));
   const OperandX8632Mem *DestMem = llvm::cast<OperandX8632Mem>(getSrc(1));
   assert(DestMem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   assert(Src->hasReg());
   Asm->movups(DestMem->toAsmAddress(Asm),
               RegX8632::getEncodedXmm(Src->getRegNum()));
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632StoreP::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storep." << getSrc(0)->getType() << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
 void InstX8632StoreQ::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   assert(getSrc(1)->getType() == IceType_i64 ||
          getSrc(1)->getType() == IceType_f64);
   Str << "\tmovq\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   getSrc(1)->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
 }
 
 void InstX8632StoreQ::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 2);
   const Variable *Src = llvm::cast<Variable>(getSrc(0));
   const OperandX8632Mem *DestMem = llvm::cast<OperandX8632Mem>(getSrc(1));
   assert(DestMem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   assert(Src->hasReg());
   Asm->movq(DestMem->toAsmAddress(Asm),
             RegX8632::getEncodedXmm(Src->getRegNum()));
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632StoreQ::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "storeq." << getSrc(0)->getType() << " ";
   getSrc(1)->dump(Func);
   Str << ", ";
   getSrc(0)->dump(Func);
 }
 
 template <> void InstX8632Lea::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->hasReg());
-  Str << "\tlea\t";
-  getDest()->emit(Func);
-  Str << ", ";
+  Str << "\tleal\t";
   Operand *Src0 = getSrc(0);
   if (Variable *VSrc0 = llvm::dyn_cast<Variable>(Src0)) {
     Type Ty = VSrc0->getType();
     // lea on x86-32 doesn't accept mem128 operands, so cast VSrc0 to an
     // acceptable type.
     VSrc0->asType(isVectorType(Ty) ? IceType_i32 : Ty).emit(Func);
   } else {
     Src0->emit(Func);
   }
+  Str << ", ";
+  getDest()->emit(Func);
 }
 
 template <> void InstX8632Mov::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Operand *Src = getSrc(0);
-  // The llvm-mc assembler using Intel syntax has a bug in which "mov
-  // reg, RelocatableConstant" does not generate the right instruction
-  // with a relocation.  To work around, we emit "lea reg,
-  // RelocatableConstant".  Also, the lowering and legalization is
-  // changed to allow relocatable constants only in Assign and Call
-  // instructions or in Mem operands.  TODO(stichnot): remove LEAHACK
-  // once a proper emitter is used.
-  //
-  // In addition, llvm-mc doesn't like "lea eax, bp" or "lea eax, Sp"
-  // or "lea eax, flags" etc., when the relocatable constant name is a
-  // reserved word.  The hack-on-top-of-hack is to temporarily drop
-  // into AT&T syntax for this lea instruction.
-  bool UseLeaHack = llvm::isa<ConstantRelocatable>(Src);
-  if (UseLeaHack) {
-    Str << ".att_syntax\n";
-    Str << "\tleal";
-  } else {
-    Str << "\tmov" << TypeX8632Attributes[getDest()->getType()].SdSsString;
-  }
-  Str << "\t";
+  Type SrcTy = Src->getType();
+  Type DestTy = getDest()->getType();
+  Str << "\tmov" << (!isScalarFloatingType(DestTy)
+                         ? getWidthString(SrcTy)
+                         : TypeX8632Attributes[DestTy].SdSsString) << "\t";
   // For an integer truncation operation, src is wider than dest.
   // Ideally, we use a mov instruction whose data width matches the
   // narrower dest.  This is a problem if e.g. src is a register like
   // esi or si where there is no 8-bit version of the register.  To be
   // safe, we instead widen the dest to match src.  This works even
   // for stack-allocated dest variables because typeWidthOnStack()
   // pads to a 4-byte boundary even if only a lower portion is used.
   // TODO: This assert disallows usages such as copying a floating point
   // value between a vector and a scalar (which movss is used for).
   // Clean this up.
-  assert(Func->getTarget()->typeWidthInBytesOnStack(getDest()->getType()) ==
-         Func->getTarget()->typeWidthInBytesOnStack(Src->getType()));
-  if (UseLeaHack) {
-    Src->emit(Func);
-    Str << ", %";
-    getDest()->emit(Func);
-    Str << "\n";
-    Str << ".intel_syntax";
-  } else {
-    getDest()->asType(Src->getType()).emit(Func);
-    Str << ", ";
-    Src->emit(Func);
-  }
+  assert(Func->getTarget()->typeWidthInBytesOnStack(DestTy) ==
+         Func->getTarget()->typeWidthInBytesOnStack(SrcTy));
+  Src->emit(Func);
+  Str << ", ";
+  getDest()->asType(SrcTy).emit(Func);
 }
 
 template <> void InstX8632Mov::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   Type DestTy = Dest->getType();
   Type SrcTy = Src->getType();
   // Mov can be used for GPRs or XMM registers. Also, the type does not
   // necessarily match (Mov can be used for bitcasts). However, when
@@ skipping 96 matching lines @@
 }
 
 template <> void InstX8632Movp::emit(const Cfg *Func) const {
   // TODO(wala,stichnot): movups works with all vector operands, but
   // there exist other instructions (movaps, movdqa, movdqu) that may
   // perform better, depending on the data type and alignment of the
   // operands.
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Str << "\tmovups\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   getDest()->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
 }
 
 template <> void InstX8632Movp::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   assert(isVectorType(getDest()->getType()));
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   const static x86::AssemblerX86::XmmEmitterMovOps Emitter = {
     &x86::AssemblerX86::movups, &x86::AssemblerX86::movups,
     &x86::AssemblerX86::movups
   };
   emitIASMovlikeXMM(Func, Dest, Src, Emitter);
 }
 
 template <> void InstX8632Movq::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   assert(getDest()->getType() == IceType_i64 ||
          getDest()->getType() == IceType_f64);
   Str << "\tmovq\t";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   getDest()->emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
 }
 
 template <> void InstX8632Movq::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 1);
   assert(getDest()->getType() == IceType_i64 ||
          getDest()->getType() == IceType_f64);
   const Variable *Dest = getDest();
   const Operand *Src = getSrc(0);
   const static x86::AssemblerX86::XmmEmitterMovOps Emitter = {
     &x86::AssemblerX86::movq, &x86::AssemblerX86::movq, &x86::AssemblerX86::movq
@@ skipping 55 matching lines @@
 
 void InstX8632Nop::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "nop (variant = " << Variant << ")";
 }
 
 void InstX8632Fld::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Type Ty = getSrc(0)->getType();
+  SizeT Width = typeWidthInBytes(Ty);
   Variable *Var = llvm::dyn_cast<Variable>(getSrc(0));
   if (Var && Var->hasReg()) {
     // This is a physical xmm register, so we need to spill it to a
     // temporary stack slot.
-    SizeT Width = typeWidthInBytes(Ty);
-    Str << "\tsub\tesp, " << Width << "\n";
-    Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t"
-        << TypeX8632Attributes[Ty].WidthString << " [esp], ";
+    Str << "\tsubl\t$" << Width << ", %esp"
+        << "\n";

[jvoung (off chromium), 2014/10/31 22:12:18]

\n could fit on the previous line next to %esp

[Jim Stichnoth, 2014/11/01 13:44:17]

Done.

+    Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t";
     Var->emit(Func);
-    Str << "\n";
-    Str << "\tfld\t" << TypeX8632Attributes[Ty].WidthString << " [esp]\n";
-    Str << "\tadd\tesp, " << Width;
+    Str << ", (%esp)\n";
+    Str << "\tfld" << getFldString(Ty) << "\t"
+        << "(%esp)\n";
+    Str << "\taddl\t$" << Width << ", %esp";
     return;
   }
-  Str << "\tfld\t";
+  Str << "\tfld" << getFldString(Ty) << "\t";
   getSrc(0)->emit(Func);
 }
 
 void InstX8632Fld::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 1);
   const Operand *Src = getSrc(0);
   Type Ty = Src->getType();
   if (const auto Var = llvm::dyn_cast<Variable>(Src)) {
@@ skipping 32 matching lines @@
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 0);
   // TODO(jvoung,stichnot): Utilize this by setting Dest to NULL to
   // "partially" delete the fstp if the Dest is unused.
   // Even if Dest is unused, the fstp should be kept for the SideEffects
   // of popping the stack.
   if (getDest() == NULL) {
     Str << "\tfstp\tst(0)";
     return;
   }
+  Type Ty = getDest()->getType();
+  size_t Width = typeWidthInBytes(Ty);
   if (!getDest()->hasReg()) {
-    Str << "\tfstp\t";
+    Str << "\tfstp" << getFldString(Ty) << "\t";
     getDest()->emit(Func);
     return;
   }
   // Dest is a physical (xmm) register, so st(0) needs to go through
   // memory.  Hack this by creating a temporary stack slot, spilling
   // st(0) there, loading it into the xmm register, and deallocating
   // the stack slot.
-  Type Ty = getDest()->getType();
-  size_t Width = typeWidthInBytes(Ty);
-  Str << "\tsub\tesp, " << Width << "\n";
-  Str << "\tfstp\t" << TypeX8632Attributes[Ty].WidthString << " [esp]\n";
-  Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t";
+  Str << "\tsubl\t$" << Width << ", %esp\n";
+  Str << "\tfstp" << getFldString(Ty) << "\t"
+      << "(%esp)\n";

[jvoung (off chromium), 2014/10/31 22:12:18]

nit: Could do the full fstp on one line like before.

[Jim Stichnoth, 2014/11/01 13:44:17]

Done.

+  Str << "\tmov" << TypeX8632Attributes[Ty].SdSsString << "\t"
+      << "(%esp), ";
   getDest()->emit(Func);
-  Str << ", " << TypeX8632Attributes[Ty].WidthString << " [esp]\n";
-  Str << "\tadd\tesp, " << Width;
+  Str << "\n";
+  Str << "\taddl\t$" << Width << ", %esp";
 }
 
 void InstX8632Fstp::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   assert(getSrcSize() == 0);
   const Variable *Dest = getDest();
   // TODO(jvoung,stichnot): Utilize this by setting Dest to NULL to
   // "partially" delete the fstp if the Dest is unused.
   // Even if Dest is unused, the fstp should be kept for the SideEffects
@@ skipping 47 matching lines @@
 template <> void InstX8632Pextr::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   assert(getSrc(0)->getType() == IceType_v8i16 ||
          getSrc(0)->getType() == IceType_v8i1 ||
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
              >= TargetX8632::SSE4_1);
   Str << "\t" << Opcode
       << TypeX8632Attributes[getSrc(0)->getType()].PackString << "\t";
+  getSrc(1)->emit(Func);
+  Str << ", ";
+  getSrc(0)->emit(Func);
+  Str << ", ";
   Variable *Dest = getDest();
   // pextrw must take a register dest. There is an SSE4.1 version that takes
   // a memory dest, but we aren't using it. For uniformity, just restrict
   // them all to have a register dest for now.
   assert(Dest->hasReg());
   Dest->asType(IceType_i32).emit(Func);
-  Str << ", ";
-  getSrc(0)->emit(Func);
-  Str << ", ";
-  getSrc(1)->emit(Func);
 }
 
 template <> void InstX8632Pextr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   const Variable *Dest = getDest();
   Type DispatchTy = Dest->getType();
   assert(DispatchTy == IceType_i16 ||
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
              TargetX8632::SSE4_1);
@@ skipping 14 matching lines @@
 template <> void InstX8632Pinsr::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 3);
   // pinsrb and pinsrd are SSE4.1 instructions.
   assert(getDest()->getType() == IceType_v8i16 ||
          getDest()->getType() == IceType_v8i1 ||
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet()
              >= TargetX8632::SSE4_1);
   Str << "\t" << Opcode
       << TypeX8632Attributes[getDest()->getType()].PackString << "\t";
-  getDest()->emit(Func);
+  getSrc(2)->emit(Func);
   Str << ", ";
   Operand *Src1 = getSrc(1);
   if (Variable *VSrc1 = llvm::dyn_cast<Variable>(Src1)) {
     // If src1 is a register, it should always be r32.
     if (VSrc1->hasReg()) {
       VSrc1->asType(IceType_i32).emit(Func);
     } else {
       VSrc1->emit(Func);
     }
   } else {
     Src1->emit(Func);
   }
   Str << ", ";
-  getSrc(2)->emit(Func);
+  getDest()->emit(Func);
 }
 
 template <> void InstX8632Pinsr::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 3);
   assert(getDest() == getSrc(0));
   // pinsrb and pinsrd are SSE4.1 instructions.
   const Operand *Src0 = getSrc(1);
   Type DispatchTy = Src0->getType();
   assert(DispatchTy == IceType_i16 ||
          static_cast<TargetX8632 *>(Func->getTarget())->getInstructionSet() >=
@@ skipping 56 matching lines @@
 }
 
 void InstX8632Pop::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   dumpDest(Func);
   Str << " = pop." << getDest()->getType() << " ";
 }
 
 void InstX8632AdjustStack::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
-  Str << "\tsub\tesp, " << Amount;
+  Str << "\tsubl\t$" << Amount << ", %esp";
   Func->getTarget()->updateStackAdjustment(Amount);
 }
 
 void InstX8632AdjustStack::emitIAS(const Cfg *Func) const {
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Asm->sub(IceType_i32, RegX8632::Encoded_Reg_esp, x86::Immediate(Amount));
   emitIASBytes(Func, Asm, StartPosition);
   Func->getTarget()->updateStackAdjustment(Amount);
 }
@@ skipping 69 matching lines @@
   Type Ty = (getSrcSize() == 0 ? IceType_void : getSrc(0)->getType());
   Str << "ret." << Ty << " ";
   dumpSources(Func);
 }
 
 void InstX8632Xadd::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   if (Locked) {
     Str << "\tlock";
   }
-  Str << "\txadd\t";
+  Str << "\txadd" << getWidthString(getSrc(0)->getType()) << "\t";
+  getSrc(1)->emit(Func);
+  Str << ", ";
   getSrc(0)->emit(Func);
-  Str << ", ";
-  getSrc(1)->emit(Func);
 }
 
 void InstX8632Xadd::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Type Ty = getSrc(0)->getType();
   const OperandX8632Mem *Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
   assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   const x86::Address Addr = Mem->toAsmAddress(Asm);
@@ skipping 13 matching lines @@
   if (Locked) {
     Str << "lock ";
   }
   Type Ty = getSrc(0)->getType();
   Str << "xadd." << Ty << " ";
   dumpSources(Func);
 }
 
 void InstX8632Xchg::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << "\txchg\t";

[jvoung (off chromium), 2014/10/31 22:12:18]

I'm surprised this doesn't have the getWidthString()

[Jim Stichnoth, 2014/11/01 13:44:16]

Good point.  It turns out that for both llvm-mc and gas (and objdump -d as
well), the b/w/l opcode suffix is optional if it can be inferred from an
explicit register operand.  E.g., "add $1, %ax" is OK, but "add $1, (%esp)" is
not.  Since the xchg instruction always has at least one register operand, it
ends up being OK to never emit the opcode suffix.

All the same, I added it for consistency.

+  getSrc(1)->emit(Func);
+  Str << ", ";
   getSrc(0)->emit(Func);
-  Str << ", ";
-  getSrc(1)->emit(Func);
 }
 
 void InstX8632Xchg::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   x86::AssemblerX86 *Asm = Func->getAssembler<x86::AssemblerX86>();
   intptr_t StartPosition = Asm->GetPosition();
   Type Ty = getSrc(0)->getType();
   const OperandX8632Mem *Mem = llvm::cast<OperandX8632Mem>(getSrc(0));
   assert(Mem->getSegmentRegister() == OperandX8632Mem::DefaultSegment);
   const x86::Address Addr = Mem->toAsmAddress(Asm);
   const Variable *VarReg = llvm::cast<Variable>(getSrc(1));
   assert(VarReg->hasReg());
   const RegX8632::GPRRegister Reg =
       RegX8632::getEncodedGPR(VarReg->getRegNum());
   Asm->xchg(Ty, Addr, Reg);
   emitIASBytes(Func, Asm, StartPosition);
 }
 
 void InstX8632Xchg::dump(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrDump();
   Type Ty = getSrc(0)->getType();
   Str << "xchg." << Ty << " ";
   dumpSources(Func);
 }
 
 void OperandX8632Mem::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
-  Str << TypeX8632Attributes[getType()].WidthString << " ";
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Str << InstX8632SegmentRegNames[SegmentReg] << ":";
   }
-  // TODO: The following is an almost verbatim paste of dump().
-  bool Dumped = false;
-  Str << "[";
+  // Emit as Offset(Base,Index,1<<Shift).
+  // Offset is emitted without the leading '$'.
+  // Omit the (Base,Index,1<<Shift) part if Base==NULL.
+  if (Offset == NULL) {
+    // No offset, emit nothing.
+  } else if (auto CI = llvm::dyn_cast<ConstantInteger32>(Offset)) {
+    if (CI->getValue())
+      // Emit a non-zero offset without a leading '$'.
+      Str << CI->getValue();
+  } else if (auto CR = llvm::dyn_cast<ConstantRelocatable>(Offset)) {
+    CR->emitWithoutDollar(Func->getContext());
+  } else {
+    assert(0);

[jvoung (off chromium), 2014/10/31 22:12:18]

could do llvm_unreachable("...")

[Jim Stichnoth, 2014/11/01 13:44:17]

Done.

+  }
+
   if (Base) {
+    Str << "(";
     Base->emit(Func);
-    Dumped = true;
+    if (Index) {
+      Str << ",";
+      Index->emit(Func);
+      if (Shift)
+        Str << "," << (1u << Shift);
+    }
+    Str << ")";
   }
-  if (Index) {
-    assert(Base);
-    Str << "+";
-    if (Shift > 0)
-      Str << (1u << Shift) << "*";
-    Index->emit(Func);
-    Dumped = true;
-  }
-  // Pretty-print the Offset.
-  bool OffsetIsZero = false;
-  bool OffsetIsNegative = false;
-  if (Offset == NULL) {
-    OffsetIsZero = true;
-  } else if (ConstantInteger32 *CI =
-                 llvm::dyn_cast<ConstantInteger32>(Offset)) {
-    OffsetIsZero = (CI->getValue() == 0);
-    OffsetIsNegative = (static_cast<int32_t>(CI->getValue()) < 0);
-  } else {
-    assert(llvm::isa<ConstantRelocatable>(Offset));
-  }
-  if (Dumped) {
-    if (!OffsetIsZero) {     // Suppress if Offset is known to be 0
-      if (!OffsetIsNegative) // Suppress if Offset is known to be negative
-        Str << "+";
-      Offset->emit(Func);
-    }
-  } else {
-    // There is only the offset.
-    Offset->emit(Func);
-  }
-  Str << "]";
 }
 
 void OperandX8632Mem::dump(const Cfg *Func, Ostream &Str) const {
   if (SegmentReg != DefaultSegment) {
     assert(SegmentReg >= 0 && SegmentReg < SegReg_NUM);
     Str << InstX8632SegmentRegNames[SegmentReg] << ":";
   }
   bool Dumped = false;
   Str << "[";
   if (Base) {
@@ skipping 89 matching lines @@
   return x86::Address(RegX8632::getEncodedGPR(Target->getFrameOrStackReg()),
                       Offset);
 }
 
 void VariableSplit::emit(const Cfg *Func) const {
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(!Var->hasReg());
   // The following is copied/adapted from TargetX8632::emitVariable().
   const TargetLowering *Target = Func->getTarget();
   const Type Ty = IceType_i32;
-  Str << TypeX8632Attributes[Ty].WidthString << " ["
-      << Target->getRegName(Target->getFrameOrStackReg(), Ty);
   int32_t Offset =
       Var->getStackOffset() + Target->getStackAdjustment() + getOffset();
-  if (Offset) {
-    if (Offset > 0)
-      Str << "+";
+  if (Offset)
     Str << Offset;
-  }
-  Str << "]";
+  Str << "(%" << Target->getRegName(Target->getFrameOrStackReg(), Ty) << ")";
 }
 
 void VariableSplit::dump(const Cfg *Func, Ostream &Str) const {
   switch (Part) {
   case Low:
     Str << "low";
     break;
   case High:
     Str << "high";
     break;
   default:
     Str << "???";
     break;
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice