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Side by Side Diff: test/unittests/compiler/instruction-selector-unittest.cc

Issue 694313002: [turbofan] add RegisterConfiguration to decouple arch specific register layouts from compiler (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "test/unittests/compiler/instruction-selector-unittest.h" 5 #include "test/unittests/compiler/instruction-selector-unittest.h"
6 6
7 #include "src/compiler/graph-inl.h" 7 #include "src/compiler/graph-inl.h"
8 #include "src/flags.h" 8 #include "src/flags.h"
9 #include "test/unittests/compiler/compiler-test-utils.h" 9 #include "test/unittests/compiler/compiler-test-utils.h"
10 10
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39 Linkage linkage(test_->zone(), call_descriptor()); 39 Linkage linkage(test_->zone(), call_descriptor());
40 InstructionBlocks* instruction_blocks = 40 InstructionBlocks* instruction_blocks =
41 InstructionSequence::InstructionBlocksFor(test_->zone(), schedule); 41 InstructionSequence::InstructionBlocksFor(test_->zone(), schedule);
42 InstructionSequence sequence(test_->zone(), instruction_blocks); 42 InstructionSequence sequence(test_->zone(), instruction_blocks);
43 SourcePositionTable source_position_table(graph()); 43 SourcePositionTable source_position_table(graph());
44 InstructionSelector selector(test_->zone(), graph(), &linkage, &sequence, 44 InstructionSelector selector(test_->zone(), graph(), &linkage, &sequence,
45 schedule, &source_position_table, features); 45 schedule, &source_position_table, features);
46 selector.SelectInstructions(); 46 selector.SelectInstructions();
47 if (FLAG_trace_turbo) { 47 if (FLAG_trace_turbo) {
48 OFStream out(stdout); 48 OFStream out(stdout);
49 PrintableInstructionSequence printable = {
50 RegisterConfiguration::ArchDefault(), &sequence};
49 out << "=== Code sequence after instruction selection ===" << std::endl 51 out << "=== Code sequence after instruction selection ===" << std::endl
50 << sequence; 52 << printable;
51 } 53 }
52 Stream s; 54 Stream s;
53 // Map virtual registers. 55 // Map virtual registers.
54 { 56 {
55 const NodeToVregMap& node_map = selector.GetNodeMapForTesting(); 57 const NodeToVregMap& node_map = selector.GetNodeMapForTesting();
56 for (int i = 0; i < initial_node_count; ++i) { 58 for (int i = 0; i < initial_node_count; ++i) {
57 if (node_map[i] != InstructionSelector::kNodeUnmapped) { 59 if (node_map[i] != InstructionSelector::kNodeUnmapped) {
58 s.virtual_registers_.insert(std::make_pair(i, node_map[i])); 60 s.virtual_registers_.insert(std::make_pair(i, node_map[i]));
59 } 61 }
60 } 62 }
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578 EXPECT_EQ(s.ToVreg(context2), s.ToVreg(call_instr->InputAt(12))); 580 EXPECT_EQ(s.ToVreg(context2), s.ToVreg(call_instr->InputAt(12)));
579 // Continuation. 581 // Continuation.
580 582
581 EXPECT_EQ(kArchRet, s[index++]->arch_opcode()); 583 EXPECT_EQ(kArchRet, s[index++]->arch_opcode());
582 EXPECT_EQ(index, s.size()); 584 EXPECT_EQ(index, s.size());
583 } 585 }
584 586
585 } // namespace compiler 587 } // namespace compiler
586 } // namespace internal 588 } // namespace internal
587 } // namespace v8 589 } // namespace v8
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