[turbofan] add RegisterConfiguration to decouple arch specific register layouts from compiler

src/compiler/pipeline.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/pipeline.h"
 
 #include <fstream>  // NOLINT(readability/streams)
 #include <sstream>
 
 #include "src/base/platform/elapsed-timer.h"
@@ skipping 540 matching lines @@
     PhaseScope phase_scope(data->pipeline_statistics(), "select instructions");
     ZonePool::Scope zone_scope(data->zone_pool());
     InstructionSelector selector(zone_scope.zone(), data->graph(), linkage,
                                  &sequence, data->schedule(),
                                  data->source_positions());
     selector.SelectInstructions();
   }
 
   if (FLAG_trace_turbo) {
     OFStream os(stdout);
+    PrintableInstructionSequence printable = {
+        RegisterConfiguration::ArchDefault(), &sequence};
     os << "----- Instruction sequence before register allocation -----\n"
-       << sequence;
+       << printable;
     TurboCfgFile tcf(isolate());
     tcf << AsC1V("CodeGen", data->schedule(), data->source_positions(),
                  &sequence);
   }
 
   data->DeleteGraphZone();
 
   if (data->pipeline_statistics() != NULL) {
     data->pipeline_statistics()->BeginPhaseKind("register allocation");
   }
 
   // Allocate registers.
   Frame frame;
   {
     int node_count = sequence.VirtualRegisterCount();
     if (node_count > UnallocatedOperand::kMaxVirtualRegisters) {
       info()->AbortOptimization(kNotEnoughVirtualRegistersForValues);
       return Handle<Code>::null();
     }
     ZonePool::Scope zone_scope(data->zone_pool());
 
     SmartArrayPointer<char> debug_name;
 #ifdef DEBUG
     debug_name = GetDebugName(info());
 #endif
 
 
-    RegisterAllocator allocator(RegisterAllocator::PlatformConfig(),
+    RegisterAllocator allocator(RegisterConfiguration::ArchDefault(),
                                 zone_scope.zone(), &frame, &sequence,
                                 debug_name.get());
     if (!allocator.Allocate(data->pipeline_statistics())) {
       info()->AbortOptimization(kNotEnoughVirtualRegistersRegalloc);
       return Handle<Code>::null();
     }
     if (FLAG_trace_turbo) {
       TurboCfgFile tcf(isolate());
       tcf << AsC1VAllocator("CodeGen", &allocator);
     }
   }
 
   if (FLAG_trace_turbo) {
     OFStream os(stdout);
+    PrintableInstructionSequence printable = {
+        RegisterConfiguration::ArchDefault(), &sequence};
     os << "----- Instruction sequence after register allocation -----\n"
-       << sequence;
+       << printable;
   }
 
   if (data->pipeline_statistics() != NULL) {
     data->pipeline_statistics()->BeginPhaseKind("code generation");
   }
 
   // Generate native sequence.
   Handle<Code> code;
   {
     PhaseScope phase_scope(data->pipeline_statistics(), "generate code");
@@ skipping 16 matching lines @@
 }
 
 
 void Pipeline::TearDown() {
   InstructionOperand::TearDownCaches();
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8