Subzero: Improve the representation and handling of the FakeKill instruction.

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 298 matching lines @@
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
 }
 
 void TargetX8632::translateO2() {
   TimerMarker T(TimerStack::TT_O2, Func);
 
+  initFakeKilledScratchRegisters();
+
   if (!Ctx->getFlags().PhiEdgeSplit) {
     // Lower Phi instructions.
     Func->placePhiLoads();
     if (Func->hasError())
       return;
     Func->placePhiStores();
     if (Func->hasError())
       return;
     Func->deletePhis();
     if (Func->hasError())
@@ skipping 75 matching lines @@
   Func->dump("After branch optimization");
 
   // Nop insertion
   if (shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
 void TargetX8632::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
+
+  initFakeKilledScratchRegisters();
+
   Func->placePhiLoads();
   if (Func->hasError())
     return;
   Func->placePhiStores();
   if (Func->hasError())
     return;
   Func->deletePhis();
   if (Func->hasError())
     return;
   Func->dump("After Phi lowering");
@@ skipping 1438 matching lines @@
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
 
   // Add the appropriate offset to esp.  The call instruction takes care
   // of resetting the stack offset during emission.
   if (ParameterAreaSizeBytes) {
     Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
     _add(esp, Ctx->getConstantInt32(IceType_i32, ParameterAreaSizeBytes));
   }
 
   // Insert a register-kill pseudo instruction.
-  VarList KilledRegs;
-  for (SizeT i = 0; i < ScratchRegs.size(); ++i) {
-    if (ScratchRegs[i])
-      KilledRegs.push_back(Func->getTarget()->getPhysicalRegister(i));
-  }
-  Context.insert(InstFakeKill::create(Func, KilledRegs, NewCall));
+  assert(!FakeKilledScratchRegisters.empty());
+  Context.insert(
+      InstFakeKill::create(Func, FakeKilledScratchRegisters, NewCall));
 
   // Generate a FakeUse to keep the call live if necessary.
   if (Instr->hasSideEffects() && ReturnReg) {
     Inst *FakeUse = InstFakeUse::create(Func, ReturnReg);
     Context.insert(FakeUse);
   }
 
   if (!Dest)
     return;
 
@@ skipping 2644 matching lines @@
       continue;
     // Don't consider a FakeKill instruction, because (currently) it
     // is only used to kill all scratch registers at a call site, and
     // we don't want to black-list all scratch registers during the
     // call lowering.  This could become a problem since it relies on
     // the lowering sequence not keeping any infinite-weight variables
     // live across a call.  TODO(stichnot): Consider replacing this
     // whole postLower() implementation with a robust local register
     // allocator, for example compute live ranges only for pre-colored
     // and infinite-weight variables and run the existing linear-scan
     // allocator.

[jvoung (off chromium), 2014/11/04 16:47:07]

Maybe this can be an assert that isa<InstFakeKill>(Inst) implies that the
NumSrcs are 0. Then the comment above will be clearer about why InstFakeKill is
brought up here, but no code checks for it anymore.

[Jim Stichnoth, 2014/11/04 17:10:39]

Done.

-    if (llvm::isa<InstFakeKill>(Inst))
-      continue;
     for (SizeT SrcNum = 0; SrcNum < Inst->getSrcSize(); ++SrcNum) {
       Operand *Src = Inst->getSrc(SrcNum);
       SizeT NumVars = Src->getNumVars();
       for (SizeT J = 0; J < NumVars; ++J) {
         const Variable *Var = Src->getVar(J);
         // Track last uses of all variables, regardless of whether
         // they are pre-colored or infinite-weight.
         LastUses[Var] = Inst;
         if (!Var->hasReg())
           continue;
         WhiteList[Var->getRegNum()] = false;
       }
     }
   }
   // The second pass colors infinite-weight variables.
   llvm::SmallBitVector AvailableRegisters = WhiteList;
   llvm::SmallBitVector FreedRegisters(WhiteList.size());
   for (Inst *Inst : Context) {
     FreedRegisters.reset();
     if (Inst->isDeleted())
       continue;
-    // Skip FakeKill instructions like above.
-    if (llvm::isa<InstFakeKill>(Inst))
-      continue;
     // Iterate over all variables referenced in the instruction,
     // including the Dest variable (if any).  If the variable is
     // marked as infinite-weight, find it a register.  If this
     // instruction is the last use of the variable in the lowered
     // sequence, release the register to the free list after this
     // instruction is completely processed.  Note that the first pass
     // ignores the Dest operand, under the assumption that a
     // pre-colored Dest will appear as a source operand in some
     // subsequent instruction in the lowered sequence.
     Variable *Dest = Inst->getDest();
     SizeT NumSrcs = Inst->getSrcSize();
     if (Dest)
       ++NumSrcs;
+    if (NumSrcs == 0)
+      continue;
     OperandList Srcs(NumSrcs);
     for (SizeT i = 0; i < Inst->getSrcSize(); ++i)
       Srcs[i] = Inst->getSrc(i);
     if (Dest)
       Srcs[NumSrcs - 1] = Dest;
     for (SizeT SrcNum = 0; SrcNum < NumSrcs; ++SrcNum) {
       Operand *Src = Srcs[SrcNum];
       SizeT NumVars = Src->getNumVars();
       for (SizeT J = 0; J < NumVars; ++J) {
         Variable *Var = Src->getVar(J);
@@ skipping 132 matching lines @@
   } else if (IsConstant || IsExternal)
     Str << "\t.zero\t" << Size << "\n";
   // Size is part of .comm.
 
   if (IsConstant || HasNonzeroInitializer || IsExternal)
     Str << "\t.size\t" << MangledName << ", " << Size << "\n";
   // Size is part of .comm.
 }
 
 } // end of namespace Ice