Turn off dump/emit routines when building minimal subzero.

src/PNaClTranslator.cpp

 //===- subzero/src/PNaClTranslator.cpp - ICE from bitcode -----------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the PNaCl bitcode file to Ice, to machine code
@@ skipping 69 matching lines @@
 protected:
   // Note: For simple types, the return type of the signature will
   // be used to hold the simple type.
   Ice::FuncSigType Signature;
 
 private:
   ExtendedType::TypeKind Kind;
 };
 
 Ice::Ostream &operator<<(Ice::Ostream &Stream, const ExtendedType &Ty) {
+  if (!ALLOW_DUMP)
+    return Stream;
   Ty.dump(Stream);
   return Stream;
 }
 
 Ice::Ostream &operator<<(Ice::Ostream &Stream, ExtendedType::TypeKind Kind) {
+  if (!ALLOW_DUMP)
+    return Stream;
   Stream << "ExtendedType::";
   switch (Kind) {
   case ExtendedType::Undefined:
     Stream << "Undefined";
     break;
   case ExtendedType::Simple:
     Stream << "Simple";
     break;
   case ExtendedType::FuncSig:
     Stream << "FuncSig";
@@ skipping 26 matching lines @@
   void setReturnType(Ice::Type ReturnType) {
     Signature.setReturnType(ReturnType);
   }
   void appendArgType(Ice::Type ArgType) { Signature.appendArgType(ArgType); }
   static bool classof(const ExtendedType *Ty) {
     return Ty->getKind() == FuncSig;
   }
 };
 
 void ExtendedType::dump(Ice::Ostream &Stream) const {
+  if (!ALLOW_DUMP)
+    return;
   Stream << Kind;
   switch (Kind) {
   case Simple: {
     Stream << " " << Signature.getReturnType();
     break;
   }
   case FuncSig: {
     Stream << " " << Signature;
   }
   default:
@@ skipping 387 matching lines @@
     return ALLOW_DISABLE_IR_GEN ? getTranslator().getFlags().DisableIRGeneration
                                 : false;
   }
 
   // Generates an error Message with the bit address prefixed to it.
   bool Error(const std::string &Message) override {
     uint64_t Bit = Record.GetStartBit() + Context->getHeaderSize() * 8;
     std::string Buffer;
     raw_string_ostream StrBuf(Buffer);
     StrBuf << "(" << format("%" PRIu64 ":%u", (Bit / 8),
-                            static_cast<unsigned>(Bit % 8)) << ") " << Message;
+                            static_cast<unsigned>(Bit % 8)) << ") ";
+    // Note: If dump routines have been turned off, the error messages
+    // will not be readable. Hence, replace with simple error.
+    if (ALLOW_DUMP)
+      StrBuf << Message;
+    else
+      StrBuf << "Invalid input record";
     return Context->Error(StrBuf.str());
   }
 
   // Default implementation. Reports that block is unknown and skips
   // its contents.
   bool ParseBlock(unsigned BlockID) override;
 
   // Default implementation. Reports that the record is not
   // understood.
   void ProcessRecord() override;
@@ skipping 828 matching lines @@
   enum VectorIndexCheckValue {
     VectorIndexNotVector,
     VectorIndexNotConstant,
     VectorIndexNotInRange,
     VectorIndexNotI32,
     VectorIndexValid
   };
 
   void dumpVectorIndexCheckValue(raw_ostream &Stream,
                                  VectorIndexCheckValue Value) const {
+    if (!ALLOW_DUMP)
+      return;
     switch (Value) {
     default:
       report_fatal_error("Unknown VectorIndexCheckValue");
       break;
     case VectorIndexNotVector:
       Stream << "Vector index on non vector";
       break;
     case VectorIndexNotConstant:
       Stream << "Vector index not integer constant";
       break;
@@ skipping 1451 matching lines @@
 
   if (TopLevelBlocks != 1) {
     errs() << IRFilename
            << ": Contains more than one module. Found: " << TopLevelBlocks
            << "\n";
     ErrorStatus = true;
   }
 }
 
 } // end of namespace Ice