OLD | NEW |
1 // Copyright 2014 The Crashpad Authors. All rights reserved. | 1 // Copyright 2014 The Crashpad Authors. All rights reserved. |
2 // | 2 // |
3 // Licensed under the Apache License, Version 2.0 (the "License"); | 3 // Licensed under the Apache License, Version 2.0 (the "License"); |
4 // you may not use this file except in compliance with the License. | 4 // you may not use this file except in compliance with the License. |
5 // You may obtain a copy of the License at | 5 // You may obtain a copy of the License at |
6 // | 6 // |
7 // http://www.apache.org/licenses/LICENSE-2.0 | 7 // http://www.apache.org/licenses/LICENSE-2.0 |
8 // | 8 // |
9 // Unless required by applicable law or agreed to in writing, software | 9 // Unless required by applicable law or agreed to in writing, software |
10 // distributed under the License is distributed on an "AS IS" BASIS, | 10 // distributed under the License is distributed on an "AS IS" BASIS, |
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
12 // See the License for the specific language governing permissions and | 12 // See the License for the specific language governing permissions and |
13 // limitations under the License. | 13 // limitations under the License. |
14 | 14 |
15 #ifndef CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ | 15 #ifndef CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ |
16 #define CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ | 16 #define CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ |
17 | 17 |
18 #include <stdint.h> | 18 #include <stdint.h> |
19 | 19 |
| 20 #include "snapshot/cpu_context.h" |
20 #include "util/numeric/int128.h" | 21 #include "util/numeric/int128.h" |
21 | 22 |
22 namespace crashpad { | 23 namespace crashpad { |
23 | 24 |
24 //! \brief Architecture-independent flags for `context_flags` fields in Minidump | 25 //! \brief Architecture-independent flags for `context_flags` fields in Minidump |
25 //! context structures. | 26 //! context structures. |
26 // | 27 // |
27 // http://zachsaw.blogspot.com/2010/11/wow64-bug-getthreadcontext-may-return.htm
l#c5639760895973344002 | 28 // http://zachsaw.blogspot.com/2010/11/wow64-bug-getthreadcontext-may-return.htm
l#c5639760895973344002 |
28 enum MinidumpContextFlags : uint32_t { | 29 enum MinidumpContextFlags : uint32_t { |
29 //! \brief The thread was executing a trap handler in kernel mode | 30 //! \brief The thread was executing a trap handler in kernel mode |
(...skipping 93 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
123 kMinidumpContextX86FloatingPoint | | 124 kMinidumpContextX86FloatingPoint | |
124 kMinidumpContextX86Debug | | 125 kMinidumpContextX86Debug | |
125 kMinidumpContextX86Extended, | 126 kMinidumpContextX86Extended, |
126 }; | 127 }; |
127 | 128 |
128 //! \brief A 32-bit x86 CPU context (register state) carried in a minidump file. | 129 //! \brief A 32-bit x86 CPU context (register state) carried in a minidump file. |
129 //! | 130 //! |
130 //! This is analogous to the `CONTEXT` structure on Windows when targeting | 131 //! This is analogous to the `CONTEXT` structure on Windows when targeting |
131 //! 32-bit x86. This structure is used instead of `CONTEXT` to make it available | 132 //! 32-bit x86. This structure is used instead of `CONTEXT` to make it available |
132 //! when targeting other architectures. | 133 //! when targeting other architectures. |
| 134 //! |
| 135 //! \note This structure doesn’t carry `dr4` or `dr5`, which are obsolete and |
| 136 //! normally alias `dr6` and `dr7`, respectively. See Intel Software |
| 137 //! Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-052), |
| 138 //! 17.2.2 “Debug Registers DR4 and DR5”. |
133 struct MinidumpContextX86 { | 139 struct MinidumpContextX86 { |
134 //! \brief A bitfield composed of values of #MinidumpContextFlags and | 140 //! \brief A bitfield composed of values of #MinidumpContextFlags and |
135 //! #MinidumpContextX86Flags. | 141 //! #MinidumpContextX86Flags. |
136 //! | 142 //! |
137 //! This field identifies the context structure as a 32-bit x86 CPU context, | 143 //! This field identifies the context structure as a 32-bit x86 CPU context, |
138 //! and indicates which other fields in the structure are valid. | 144 //! and indicates which other fields in the structure are valid. |
139 uint32_t context_flags; | 145 uint32_t context_flags; |
140 | 146 |
141 uint32_t dr0; | 147 uint32_t dr0; |
142 uint32_t dr1; | 148 uint32_t dr1; |
(...skipping 26 matching lines...) Expand all Loading... |
169 uint32_t ecx; | 175 uint32_t ecx; |
170 uint32_t eax; | 176 uint32_t eax; |
171 | 177 |
172 uint32_t ebp; | 178 uint32_t ebp; |
173 uint32_t eip; | 179 uint32_t eip; |
174 uint32_t cs; | 180 uint32_t cs; |
175 uint32_t eflags; | 181 uint32_t eflags; |
176 uint32_t esp; | 182 uint32_t esp; |
177 uint32_t ss; | 183 uint32_t ss; |
178 | 184 |
179 uint8_t extended_registers[512]; | 185 // CPUContextX86::Fxsave has identical layout to what the x86 CONTEXT |
| 186 // structure places here. |
| 187 CPUContextX86::Fxsave fxsave; |
180 }; | 188 }; |
181 | 189 |
182 //! \brief x86_64-specifc flags for MinidumpContextAMD64::context_flags. | 190 //! \brief x86_64-specifc flags for MinidumpContextAMD64::context_flags. |
183 enum MinidumpContextAMD64Flags : uint32_t { | 191 enum MinidumpContextAMD64Flags : uint32_t { |
184 //! \brief Identifies the context structure as x86_64. This is the same as | 192 //! \brief Identifies the context structure as x86_64. This is the same as |
185 //! `CONTEXT_AMD64` on Windows for this architecture. | 193 //! `CONTEXT_AMD64` on Windows for this architecture. |
186 kMinidumpContextAMD64 = 0x00100000, | 194 kMinidumpContextAMD64 = 0x00100000, |
187 | 195 |
188 //! \brief Indicates the validity of control registers (`CONTEXT_CONTROL`). | 196 //! \brief Indicates the validity of control registers (`CONTEXT_CONTROL`). |
189 //! | 197 //! |
(...skipping 43 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
233 kMinidumpContextAMD64Segment | | 241 kMinidumpContextAMD64Segment | |
234 kMinidumpContextAMD64Debug, | 242 kMinidumpContextAMD64Debug, |
235 }; | 243 }; |
236 | 244 |
237 //! \brief An x86_64 (AMD64) CPU context (register state) carried in a minidump | 245 //! \brief An x86_64 (AMD64) CPU context (register state) carried in a minidump |
238 //! file. | 246 //! file. |
239 //! | 247 //! |
240 //! This is analogous to the `CONTEXT` structure on Windows when targeting | 248 //! This is analogous to the `CONTEXT` structure on Windows when targeting |
241 //! x86_64. This structure is used instead of `CONTEXT` to make it available | 249 //! x86_64. This structure is used instead of `CONTEXT` to make it available |
242 //! when targeting other architectures. | 250 //! when targeting other architectures. |
| 251 //! |
| 252 //! \note This structure doesn’t carry `dr4` or `dr5`, which are obsolete and |
| 253 //! normally alias `dr6` and `dr7`, respectively. See Intel Software |
| 254 //! Developer’s Manual, Volume 3B: System Programming, Part 2 (253669-052), |
| 255 //! 17.2.2 “Debug Registers DR4 and DR5”. |
243 struct __attribute__((aligned(16))) MinidumpContextAMD64 { | 256 struct __attribute__((aligned(16))) MinidumpContextAMD64 { |
244 //! \brief Register parameter home address. | 257 //! \brief Register parameter home address. |
245 //! | 258 //! |
246 //! On Windows, this field may contain the “home” address (on-stack, in the | 259 //! On Windows, this field may contain the “home” address (on-stack, in the |
247 //! shadow area) of a parameter passed by register. This field is present for | 260 //! shadow area) of a parameter passed by register. This field is present for |
248 //! convenience but is not necessarily populated, even if a corresponding | 261 //! convenience but is not necessarily populated, even if a corresponding |
249 //! parameter was passed by register. | 262 //! parameter was passed by register. |
250 //! | 263 //! |
251 //! \{ | 264 //! \{ |
252 uint64_t p1_home; | 265 uint64_t p1_home; |
(...skipping 41 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
294 uint64_t r9; | 307 uint64_t r9; |
295 uint64_t r10; | 308 uint64_t r10; |
296 uint64_t r11; | 309 uint64_t r11; |
297 uint64_t r12; | 310 uint64_t r12; |
298 uint64_t r13; | 311 uint64_t r13; |
299 uint64_t r14; | 312 uint64_t r14; |
300 uint64_t r15; | 313 uint64_t r15; |
301 | 314 |
302 uint64_t rip; | 315 uint64_t rip; |
303 | 316 |
304 union { | 317 // CPUContextX86_64::Fxsave has identical layout to what the x86_64 CONTEXT |
305 struct { | 318 // structure places here. |
306 uint16_t control_word; | 319 CPUContextX86_64::Fxsave fxsave; |
307 uint16_t status_word; | |
308 uint8_t tag_word; | |
309 uint8_t reserved_1; | |
310 uint16_t error_opcode; | |
311 uint32_t error_offset; | |
312 uint16_t error_selector; | |
313 uint16_t reserved_2; | |
314 uint32_t data_offset; | |
315 uint16_t data_selector; | |
316 uint16_t reserved_3; | |
317 uint32_t mx_csr; | |
318 uint32_t mx_csr_mask; | |
319 uint128_struct float_registers[8]; | |
320 uint128_struct xmm_registers[16]; | |
321 uint8_t reserved_4[96]; | |
322 } float_save; | |
323 struct { | |
324 uint128_struct header[2]; | |
325 uint128_struct legacy[8]; | |
326 uint128_struct xmm0; | |
327 uint128_struct xmm1; | |
328 uint128_struct xmm2; | |
329 uint128_struct xmm3; | |
330 uint128_struct xmm4; | |
331 uint128_struct xmm5; | |
332 uint128_struct xmm6; | |
333 uint128_struct xmm7; | |
334 uint128_struct xmm8; | |
335 uint128_struct xmm9; | |
336 uint128_struct xmm10; | |
337 uint128_struct xmm11; | |
338 uint128_struct xmm12; | |
339 uint128_struct xmm13; | |
340 uint128_struct xmm14; | |
341 uint128_struct xmm15; | |
342 }; | |
343 }; | |
344 | 320 |
345 uint128_struct vector_register[26]; | 321 uint128_struct vector_register[26]; |
346 uint64_t vector_control; | 322 uint64_t vector_control; |
347 | 323 |
348 //! \brief Model-specific debug extension register. | 324 //! \brief Model-specific debug extension register. |
349 //! | 325 //! |
350 //! See Intel Software Developer’s Manual, Volume 3B: System Programming, Part | 326 //! See Intel Software Developer’s Manual, Volume 3B: System Programming, Part |
351 //! 2 (253669-051), 17.4 “Last Branch, Interrupt, and Exception Recording | 327 //! 2 (253669-051), 17.4 “Last Branch, Interrupt, and Exception Recording |
352 //! Overview”, and AMD Architecture Programmer’s Manual, Volume 2: | 328 //! Overview”, and AMD Architecture Programmer’s Manual, Volume 2: |
353 //! System Programming (24593-3.24), 13.1.6 “Control-Transfer Breakpoint | 329 //! System Programming (24593-3.24), 13.1.6 “Control-Transfer Breakpoint |
354 //! Features”. | 330 //! Features”. |
355 //! | 331 //! |
356 //! \{ | 332 //! \{ |
357 uint64_t debug_control; | 333 uint64_t debug_control; |
358 uint64_t last_branch_to_rip; | 334 uint64_t last_branch_to_rip; |
359 uint64_t last_branch_from_rip; | 335 uint64_t last_branch_from_rip; |
360 uint64_t last_exception_to_rip; | 336 uint64_t last_exception_to_rip; |
361 uint64_t last_exception_from_rip; | 337 uint64_t last_exception_from_rip; |
362 //! \} | 338 //! \} |
363 }; | 339 }; |
364 | 340 |
365 } // namespace crashpad | 341 } // namespace crashpad |
366 | 342 |
367 #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ | 343 #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ |
OLD | NEW |