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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1272 const double src2, | 1272 const double src2, |
1273 const Condition cond = al); | 1273 const Condition cond = al); |
1274 void vmrs(const Register dst, | 1274 void vmrs(const Register dst, |
1275 const Condition cond = al); | 1275 const Condition cond = al); |
1276 void vmsr(const Register dst, | 1276 void vmsr(const Register dst, |
1277 const Condition cond = al); | 1277 const Condition cond = al); |
1278 void vsqrt(const DwVfpRegister dst, | 1278 void vsqrt(const DwVfpRegister dst, |
1279 const DwVfpRegister src, | 1279 const DwVfpRegister src, |
1280 const Condition cond = al); | 1280 const Condition cond = al); |
1281 | 1281 |
| 1282 // ARMv8 rounding instructions. |
| 1283 void vrinta(const DwVfpRegister dst, const DwVfpRegister src); |
| 1284 void vrintn(const DwVfpRegister dst, const DwVfpRegister src); |
| 1285 void vrintm(const DwVfpRegister dst, const DwVfpRegister src); |
| 1286 void vrintp(const DwVfpRegister dst, const DwVfpRegister src); |
| 1287 void vrintz(const DwVfpRegister dst, const DwVfpRegister src, |
| 1288 const Condition cond = al); |
| 1289 |
1282 // Support for NEON. | 1290 // Support for NEON. |
1283 // All these APIs support D0 to D31 and Q0 to Q15. | 1291 // All these APIs support D0 to D31 and Q0 to Q15. |
1284 | 1292 |
1285 void vld1(NeonSize size, | 1293 void vld1(NeonSize size, |
1286 const NeonListOperand& dst, | 1294 const NeonListOperand& dst, |
1287 const NeonMemOperand& src); | 1295 const NeonMemOperand& src); |
1288 void vst1(NeonSize size, | 1296 void vst1(NeonSize size, |
1289 const NeonListOperand& src, | 1297 const NeonListOperand& src, |
1290 const NeonMemOperand& dst); | 1298 const NeonMemOperand& dst); |
1291 void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src); | 1299 void vmovl(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src); |
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1659 public: | 1667 public: |
1660 explicit EnsureSpace(Assembler* assembler) { | 1668 explicit EnsureSpace(Assembler* assembler) { |
1661 assembler->CheckBuffer(); | 1669 assembler->CheckBuffer(); |
1662 } | 1670 } |
1663 }; | 1671 }; |
1664 | 1672 |
1665 | 1673 |
1666 } } // namespace v8::internal | 1674 } } // namespace v8::internal |
1667 | 1675 |
1668 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1676 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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