Subzero: Allow delaying Phi lowering until after register allocation.

src/IceTargetLowering.h

 //===- subzero/src/IceTargetLowering.h - Lowering interface -----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the TargetLowering and LoweringContext
@@ skipping 46 matching lines @@
   bool atEnd() const { return Cur == End; }
   InstList::iterator getCur() const { return Cur; }
   InstList::iterator getEnd() const { return End; }
   // Adaptor to enable range-based for loops.
   InstList::iterator begin() const { return getCur(); }
   InstList::iterator end() const { return getEnd(); }
   void insert(Inst *Inst);
   Inst *getLastInserted() const;
   void advanceCur() { Cur = Next; }
   void advanceNext() { advanceForward(Next); }
+  void rewind();
   void setInsertPoint(const InstList::iterator &Position) { Next = Position; }
 
 private:
   // Node is the argument to Inst::updateVars().
   CfgNode *Node;
   Inst *LastInserted;
   // Cur points to the current instruction being considered.  It is
   // guaranteed to point to a non-deleted instruction, or to be End.
   InstList::iterator Cur;
   // Next doubles as a pointer to the next valid instruction (if any),
@@ skipping 50 matching lines @@
     Func->setError("Target doesn't specify O1 lowering steps.");
   }
   virtual void translateO2() {
     Func->setError("Target doesn't specify O2 lowering steps.");
   }
 
   // Tries to do address mode optimization on a single instruction.
   void doAddressOpt();
   // Randomly insert NOPs.
   void doNopInsertion();
-  // Lowers a single instruction.
+  // Lowers a single non-Phi instruction.
   void lower();
+  // Does preliminary lowering of the set of Phi instructions in the
+  // current node.  The main intention is to do what's needed to keep
+  // the unlowered Phi instructions consistent with the lowered
+  // non-Phi instructions, e.g. to lower 64-bit operands on a 32-bit
+  // target.
+  virtual void prelowerPhis() {}
+  // Lowers a list of "parallel" assignment instructions representing
+  // a topological sort of the Phi instructions.
+  virtual void lowerPhiAssignments(CfgNode *Node,
+                                   const AssignList &Assignments) = 0;
   // Tries to do branch optimization on a single instruction.  Returns
   // true if some optimization was done.
   virtual bool doBranchOpt(Inst * /*I*/, const CfgNode * /*NextNode*/) {
     return false;
   }
 
   // Returns a variable pre-colored to the specified physical
   // register.  This is generally used to get very direct access to
   // the register such as in the prolog or epilog or for marking
   // scratch registers as killed by a call.  If a Type is not
@@ skipping 108 matching lines @@
   virtual void lower(const VariableDeclaration &Var) = 0;
 
 protected:
   TargetGlobalInitLowering(GlobalContext *Ctx) : Ctx(Ctx) {}
   GlobalContext *Ctx;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERING_H