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Issue 6794050: Revert "[Arguments] Merge (7442,7496] from bleeding_edge." (Closed) Base URL: https://v8.googlecode.com/svn/branches/experimental/arguments
Patch Set: Created 9 years, 8 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
(...skipping 30 matching lines...) Expand all
41 #include "disassembler.h" 41 #include "disassembler.h"
42 #include "macro-assembler.h" 42 #include "macro-assembler.h"
43 #include "serialize.h" 43 #include "serialize.h"
44 44
45 namespace v8 { 45 namespace v8 {
46 namespace internal { 46 namespace internal {
47 47
48 // ----------------------------------------------------------------------------- 48 // -----------------------------------------------------------------------------
49 // Implementation of CpuFeatures 49 // Implementation of CpuFeatures
50 50
51 #ifdef DEBUG 51 CpuFeatures::CpuFeatures()
52 bool CpuFeatures::initialized_ = false; 52 : supported_(0),
53 #endif 53 enabled_(0),
54 uint64_t CpuFeatures::supported_ = 0; 54 found_by_runtime_probing_(0) {
55 uint64_t CpuFeatures::found_by_runtime_probing_ = 0; 55 }
56 56
57 57
58 void CpuFeatures::Probe() { 58 // The Probe method needs executable memory, so it uses Heap::CreateCode.
59 ASSERT(!initialized_); 59 // Allocation failure is silent and leads to safe default.
60 void CpuFeatures::Probe(bool portable) {
61 ASSERT(HEAP->HasBeenSetup());
60 ASSERT(supported_ == 0); 62 ASSERT(supported_ == 0);
61 #ifdef DEBUG 63 if (portable && Serializer::enabled()) {
62 initialized_ = true;
63 #endif
64 if (Serializer::enabled()) {
65 supported_ |= OS::CpuFeaturesImpliedByPlatform(); 64 supported_ |= OS::CpuFeaturesImpliedByPlatform();
66 return; // No features if we might serialize. 65 return; // No features if we might serialize.
67 } 66 }
68 67
69 const int kBufferSize = 4 * KB; 68 Assembler assm(NULL, 0);
70 VirtualMemory* memory = new VirtualMemory(kBufferSize);
71 if (!memory->IsReserved()) {
72 delete memory;
73 return;
74 }
75 ASSERT(memory->size() >= static_cast<size_t>(kBufferSize));
76 if (!memory->Commit(memory->address(), kBufferSize, true/*executable*/)) {
77 delete memory;
78 return;
79 }
80
81 Assembler assm(NULL, memory->address(), kBufferSize);
82 Label cpuid, done; 69 Label cpuid, done;
83 #define __ assm. 70 #define __ assm.
84 // Save old esp, since we are going to modify the stack. 71 // Save old esp, since we are going to modify the stack.
85 __ push(ebp); 72 __ push(ebp);
86 __ pushfd(); 73 __ pushfd();
87 __ push(ecx); 74 __ push(ecx);
88 __ push(ebx); 75 __ push(ebx);
89 __ mov(ebp, Operand(esp)); 76 __ mov(ebp, Operand(esp));
90 77
91 // If we can modify bit 21 of the EFLAGS register, then CPUID is supported. 78 // If we can modify bit 21 of the EFLAGS register, then CPUID is supported.
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
125 // Done. 112 // Done.
126 __ bind(&done); 113 __ bind(&done);
127 __ mov(esp, Operand(ebp)); 114 __ mov(esp, Operand(ebp));
128 __ pop(ebx); 115 __ pop(ebx);
129 __ pop(ecx); 116 __ pop(ecx);
130 __ popfd(); 117 __ popfd();
131 __ pop(ebp); 118 __ pop(ebp);
132 __ ret(0); 119 __ ret(0);
133 #undef __ 120 #undef __
134 121
122 CodeDesc desc;
123 assm.GetCode(&desc);
124 Object* code;
125 { MaybeObject* maybe_code =
126 assm.isolate()->heap()->CreateCode(desc,
127 Code::ComputeFlags(Code::STUB),
128 Handle<Code>::null());
129 if (!maybe_code->ToObject(&code)) return;
130 }
131 if (!code->IsCode()) return;
132
133 PROFILE(ISOLATE,
134 CodeCreateEvent(Logger::BUILTIN_TAG,
135 Code::cast(code), "CpuFeatures::Probe"));
135 typedef uint64_t (*F0)(); 136 typedef uint64_t (*F0)();
136 F0 probe = FUNCTION_CAST<F0>(reinterpret_cast<Address>(memory->address())); 137 F0 probe = FUNCTION_CAST<F0>(Code::cast(code)->entry());
137 supported_ = probe(); 138 supported_ = probe();
138 found_by_runtime_probing_ = supported_; 139 found_by_runtime_probing_ = supported_;
139 uint64_t os_guarantees = OS::CpuFeaturesImpliedByPlatform(); 140 uint64_t os_guarantees = OS::CpuFeaturesImpliedByPlatform();
140 supported_ |= os_guarantees; 141 supported_ |= os_guarantees;
141 found_by_runtime_probing_ &= ~os_guarantees; 142 found_by_runtime_probing_ &= portable ? ~os_guarantees : 0;
142
143 delete memory;
144 } 143 }
145 144
146 145
147 // ----------------------------------------------------------------------------- 146 // -----------------------------------------------------------------------------
148 // Implementation of Displacement 147 // Implementation of Displacement
149 148
150 void Displacement::init(Label* L, Type type) { 149 void Displacement::init(Label* L, Type type) {
151 ASSERT(!L->is_bound()); 150 ASSERT(!L->is_bound());
152 int next = 0; 151 int next = 0;
153 if (L->is_linked()) { 152 if (L->is_linked()) {
(...skipping 137 matching lines...) Expand 10 before | Expand all | Expand 10 after
291 290
292 // Emit a single byte. Must always be inlined. 291 // Emit a single byte. Must always be inlined.
293 #define EMIT(x) \ 292 #define EMIT(x) \
294 *pc_++ = (x) 293 *pc_++ = (x)
295 294
296 295
297 #ifdef GENERATED_CODE_COVERAGE 296 #ifdef GENERATED_CODE_COVERAGE
298 static void InitCoverageLog(); 297 static void InitCoverageLog();
299 #endif 298 #endif
300 299
301 Assembler::Assembler(Isolate* arg_isolate, void* buffer, int buffer_size) 300 Assembler::Assembler(void* buffer, int buffer_size)
302 : AssemblerBase(arg_isolate), 301 : AssemblerBase(Isolate::Current()),
303 positions_recorder_(this), 302 positions_recorder_(this),
304 emit_debug_code_(FLAG_debug_code) { 303 emit_debug_code_(FLAG_debug_code) {
305 if (buffer == NULL) { 304 if (buffer == NULL) {
306 // Do our own buffer management. 305 // Do our own buffer management.
307 if (buffer_size <= kMinimalBufferSize) { 306 if (buffer_size <= kMinimalBufferSize) {
308 buffer_size = kMinimalBufferSize; 307 buffer_size = kMinimalBufferSize;
309 308
310 if (isolate()->assembler_spare_buffer() != NULL) { 309 if (isolate()->assembler_spare_buffer() != NULL) {
311 buffer = isolate()->assembler_spare_buffer(); 310 buffer = isolate()->assembler_spare_buffer();
312 isolate()->set_assembler_spare_buffer(NULL); 311 isolate()->set_assembler_spare_buffer(NULL);
(...skipping 67 matching lines...) Expand 10 before | Expand all | Expand 10 after
380 } 379 }
381 } 380 }
382 381
383 382
384 void Assembler::CodeTargetAlign() { 383 void Assembler::CodeTargetAlign() {
385 Align(16); // Preferred alignment of jump targets on ia32. 384 Align(16); // Preferred alignment of jump targets on ia32.
386 } 385 }
387 386
388 387
389 void Assembler::cpuid() { 388 void Assembler::cpuid() {
390 ASSERT(CpuFeatures::IsEnabled(CPUID)); 389 ASSERT(isolate()->cpu_features()->IsEnabled(CPUID));
391 EnsureSpace ensure_space(this); 390 EnsureSpace ensure_space(this);
392 last_pc_ = pc_; 391 last_pc_ = pc_;
393 EMIT(0x0F); 392 EMIT(0x0F);
394 EMIT(0xA2); 393 EMIT(0xA2);
395 } 394 }
396 395
397 396
398 void Assembler::pushad() { 397 void Assembler::pushad() {
399 EnsureSpace ensure_space(this); 398 EnsureSpace ensure_space(this);
400 last_pc_ = pc_; 399 last_pc_ = pc_;
(...skipping 340 matching lines...) Expand 10 before | Expand all | Expand 10 after
741 void Assembler::movzx_w(Register dst, const Operand& src) { 740 void Assembler::movzx_w(Register dst, const Operand& src) {
742 EnsureSpace ensure_space(this); 741 EnsureSpace ensure_space(this);
743 last_pc_ = pc_; 742 last_pc_ = pc_;
744 EMIT(0x0F); 743 EMIT(0x0F);
745 EMIT(0xB7); 744 EMIT(0xB7);
746 emit_operand(dst, src); 745 emit_operand(dst, src);
747 } 746 }
748 747
749 748
750 void Assembler::cmov(Condition cc, Register dst, int32_t imm32) { 749 void Assembler::cmov(Condition cc, Register dst, int32_t imm32) {
751 ASSERT(CpuFeatures::IsEnabled(CMOV)); 750 ASSERT(isolate()->cpu_features()->IsEnabled(CMOV));
752 EnsureSpace ensure_space(this); 751 EnsureSpace ensure_space(this);
753 last_pc_ = pc_; 752 last_pc_ = pc_;
754 UNIMPLEMENTED(); 753 UNIMPLEMENTED();
755 USE(cc); 754 USE(cc);
756 USE(dst); 755 USE(dst);
757 USE(imm32); 756 USE(imm32);
758 } 757 }
759 758
760 759
761 void Assembler::cmov(Condition cc, Register dst, Handle<Object> handle) { 760 void Assembler::cmov(Condition cc, Register dst, Handle<Object> handle) {
762 ASSERT(CpuFeatures::IsEnabled(CMOV)); 761 ASSERT(isolate()->cpu_features()->IsEnabled(CMOV));
763 EnsureSpace ensure_space(this); 762 EnsureSpace ensure_space(this);
764 last_pc_ = pc_; 763 last_pc_ = pc_;
765 UNIMPLEMENTED(); 764 UNIMPLEMENTED();
766 USE(cc); 765 USE(cc);
767 USE(dst); 766 USE(dst);
768 USE(handle); 767 USE(handle);
769 } 768 }
770 769
771 770
772 void Assembler::cmov(Condition cc, Register dst, const Operand& src) { 771 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
773 ASSERT(CpuFeatures::IsEnabled(CMOV)); 772 ASSERT(isolate()->cpu_features()->IsEnabled(CMOV));
774 EnsureSpace ensure_space(this); 773 EnsureSpace ensure_space(this);
775 last_pc_ = pc_; 774 last_pc_ = pc_;
776 // Opcode: 0f 40 + cc /r. 775 // Opcode: 0f 40 + cc /r.
777 EMIT(0x0F); 776 EMIT(0x0F);
778 EMIT(0x40 + cc); 777 EMIT(0x40 + cc);
779 emit_operand(dst, src); 778 emit_operand(dst, src);
780 } 779 }
781 780
782 781
783 void Assembler::cld() { 782 void Assembler::cld() {
(...skipping 660 matching lines...) Expand 10 before | Expand all | Expand 10 after
1444 1443
1445 1444
1446 void Assembler::nop() { 1445 void Assembler::nop() {
1447 EnsureSpace ensure_space(this); 1446 EnsureSpace ensure_space(this);
1448 last_pc_ = pc_; 1447 last_pc_ = pc_;
1449 EMIT(0x90); 1448 EMIT(0x90);
1450 } 1449 }
1451 1450
1452 1451
1453 void Assembler::rdtsc() { 1452 void Assembler::rdtsc() {
1454 ASSERT(CpuFeatures::IsEnabled(RDTSC)); 1453 ASSERT(isolate()->cpu_features()->IsEnabled(RDTSC));
1455 EnsureSpace ensure_space(this); 1454 EnsureSpace ensure_space(this);
1456 last_pc_ = pc_; 1455 last_pc_ = pc_;
1457 EMIT(0x0F); 1456 EMIT(0x0F);
1458 EMIT(0x31); 1457 EMIT(0x31);
1459 } 1458 }
1460 1459
1461 1460
1462 void Assembler::ret(int imm16) { 1461 void Assembler::ret(int imm16) {
1463 EnsureSpace ensure_space(this); 1462 EnsureSpace ensure_space(this);
1464 last_pc_ = pc_; 1463 last_pc_ = pc_;
(...skipping 385 matching lines...) Expand 10 before | Expand all | Expand 10 after
1850 1849
1851 void Assembler::fistp_s(const Operand& adr) { 1850 void Assembler::fistp_s(const Operand& adr) {
1852 EnsureSpace ensure_space(this); 1851 EnsureSpace ensure_space(this);
1853 last_pc_ = pc_; 1852 last_pc_ = pc_;
1854 EMIT(0xDB); 1853 EMIT(0xDB);
1855 emit_operand(ebx, adr); 1854 emit_operand(ebx, adr);
1856 } 1855 }
1857 1856
1858 1857
1859 void Assembler::fisttp_s(const Operand& adr) { 1858 void Assembler::fisttp_s(const Operand& adr) {
1860 ASSERT(CpuFeatures::IsEnabled(SSE3)); 1859 ASSERT(isolate()->cpu_features()->IsEnabled(SSE3));
1861 EnsureSpace ensure_space(this); 1860 EnsureSpace ensure_space(this);
1862 last_pc_ = pc_; 1861 last_pc_ = pc_;
1863 EMIT(0xDB); 1862 EMIT(0xDB);
1864 emit_operand(ecx, adr); 1863 emit_operand(ecx, adr);
1865 } 1864 }
1866 1865
1867 1866
1868 void Assembler::fisttp_d(const Operand& adr) { 1867 void Assembler::fisttp_d(const Operand& adr) {
1869 ASSERT(CpuFeatures::IsEnabled(SSE3)); 1868 ASSERT(isolate()->cpu_features()->IsEnabled(SSE3));
1870 EnsureSpace ensure_space(this); 1869 EnsureSpace ensure_space(this);
1871 last_pc_ = pc_; 1870 last_pc_ = pc_;
1872 EMIT(0xDD); 1871 EMIT(0xDD);
1873 emit_operand(ecx, adr); 1872 emit_operand(ecx, adr);
1874 } 1873 }
1875 1874
1876 1875
1877 void Assembler::fist_s(const Operand& adr) { 1876 void Assembler::fist_s(const Operand& adr) {
1878 EnsureSpace ensure_space(this); 1877 EnsureSpace ensure_space(this);
1879 last_pc_ = pc_; 1878 last_pc_ = pc_;
(...skipping 248 matching lines...) Expand 10 before | Expand all | Expand 10 after
2128 ASSERT(reg.is_byte_register()); 2127 ASSERT(reg.is_byte_register());
2129 EnsureSpace ensure_space(this); 2128 EnsureSpace ensure_space(this);
2130 last_pc_ = pc_; 2129 last_pc_ = pc_;
2131 EMIT(0x0F); 2130 EMIT(0x0F);
2132 EMIT(0x90 | cc); 2131 EMIT(0x90 | cc);
2133 EMIT(0xC0 | reg.code()); 2132 EMIT(0xC0 | reg.code());
2134 } 2133 }
2135 2134
2136 2135
2137 void Assembler::cvttss2si(Register dst, const Operand& src) { 2136 void Assembler::cvttss2si(Register dst, const Operand& src) {
2138 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2137 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2139 EnsureSpace ensure_space(this); 2138 EnsureSpace ensure_space(this);
2140 last_pc_ = pc_; 2139 last_pc_ = pc_;
2141 EMIT(0xF3); 2140 EMIT(0xF3);
2142 EMIT(0x0F); 2141 EMIT(0x0F);
2143 EMIT(0x2C); 2142 EMIT(0x2C);
2144 emit_operand(dst, src); 2143 emit_operand(dst, src);
2145 } 2144 }
2146 2145
2147 2146
2148 void Assembler::cvttsd2si(Register dst, const Operand& src) { 2147 void Assembler::cvttsd2si(Register dst, const Operand& src) {
2149 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2148 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2150 EnsureSpace ensure_space(this); 2149 EnsureSpace ensure_space(this);
2151 last_pc_ = pc_; 2150 last_pc_ = pc_;
2152 EMIT(0xF2); 2151 EMIT(0xF2);
2153 EMIT(0x0F); 2152 EMIT(0x0F);
2154 EMIT(0x2C); 2153 EMIT(0x2C);
2155 emit_operand(dst, src); 2154 emit_operand(dst, src);
2156 } 2155 }
2157 2156
2158 2157
2159 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) { 2158 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
2160 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2159 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2161 EnsureSpace ensure_space(this); 2160 EnsureSpace ensure_space(this);
2162 last_pc_ = pc_; 2161 last_pc_ = pc_;
2163 EMIT(0xF2); 2162 EMIT(0xF2);
2164 EMIT(0x0F); 2163 EMIT(0x0F);
2165 EMIT(0x2A); 2164 EMIT(0x2A);
2166 emit_sse_operand(dst, src); 2165 emit_sse_operand(dst, src);
2167 } 2166 }
2168 2167
2169 2168
2170 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 2169 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
2171 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2170 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2172 EnsureSpace ensure_space(this); 2171 EnsureSpace ensure_space(this);
2173 last_pc_ = pc_; 2172 last_pc_ = pc_;
2174 EMIT(0xF3); 2173 EMIT(0xF3);
2175 EMIT(0x0F); 2174 EMIT(0x0F);
2176 EMIT(0x5A); 2175 EMIT(0x5A);
2177 emit_sse_operand(dst, src); 2176 emit_sse_operand(dst, src);
2178 } 2177 }
2179 2178
2180 2179
2181 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 2180 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
2182 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2181 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2183 EnsureSpace ensure_space(this); 2182 EnsureSpace ensure_space(this);
2184 last_pc_ = pc_; 2183 last_pc_ = pc_;
2185 EMIT(0xF2); 2184 EMIT(0xF2);
2186 EMIT(0x0F); 2185 EMIT(0x0F);
2187 EMIT(0x5A); 2186 EMIT(0x5A);
2188 emit_sse_operand(dst, src); 2187 emit_sse_operand(dst, src);
2189 } 2188 }
2190 2189
2191 2190
2192 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 2191 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
2193 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2192 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2194 EnsureSpace ensure_space(this); 2193 EnsureSpace ensure_space(this);
2195 last_pc_ = pc_; 2194 last_pc_ = pc_;
2196 EMIT(0xF2); 2195 EMIT(0xF2);
2197 EMIT(0x0F); 2196 EMIT(0x0F);
2198 EMIT(0x58); 2197 EMIT(0x58);
2199 emit_sse_operand(dst, src); 2198 emit_sse_operand(dst, src);
2200 } 2199 }
2201 2200
2202 2201
2203 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 2202 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2204 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2203 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2205 EnsureSpace ensure_space(this); 2204 EnsureSpace ensure_space(this);
2206 last_pc_ = pc_; 2205 last_pc_ = pc_;
2207 EMIT(0xF2); 2206 EMIT(0xF2);
2208 EMIT(0x0F); 2207 EMIT(0x0F);
2209 EMIT(0x59); 2208 EMIT(0x59);
2210 emit_sse_operand(dst, src); 2209 emit_sse_operand(dst, src);
2211 } 2210 }
2212 2211
2213 2212
2214 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 2213 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2215 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2214 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2216 EnsureSpace ensure_space(this); 2215 EnsureSpace ensure_space(this);
2217 last_pc_ = pc_; 2216 last_pc_ = pc_;
2218 EMIT(0xF2); 2217 EMIT(0xF2);
2219 EMIT(0x0F); 2218 EMIT(0x0F);
2220 EMIT(0x5C); 2219 EMIT(0x5C);
2221 emit_sse_operand(dst, src); 2220 emit_sse_operand(dst, src);
2222 } 2221 }
2223 2222
2224 2223
2225 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 2224 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2226 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2225 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2227 EnsureSpace ensure_space(this); 2226 EnsureSpace ensure_space(this);
2228 last_pc_ = pc_; 2227 last_pc_ = pc_;
2229 EMIT(0xF2); 2228 EMIT(0xF2);
2230 EMIT(0x0F); 2229 EMIT(0x0F);
2231 EMIT(0x5E); 2230 EMIT(0x5E);
2232 emit_sse_operand(dst, src); 2231 emit_sse_operand(dst, src);
2233 } 2232 }
2234 2233
2235 2234
2236 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 2235 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2237 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2236 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2238 EnsureSpace ensure_space(this); 2237 EnsureSpace ensure_space(this);
2239 last_pc_ = pc_; 2238 last_pc_ = pc_;
2240 EMIT(0x66); 2239 EMIT(0x66);
2241 EMIT(0x0F); 2240 EMIT(0x0F);
2242 EMIT(0x57); 2241 EMIT(0x57);
2243 emit_sse_operand(dst, src); 2242 emit_sse_operand(dst, src);
2244 } 2243 }
2245 2244
2246 2245
2247 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 2246 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
(...skipping 10 matching lines...) Expand all
2258 EnsureSpace ensure_space(this); 2257 EnsureSpace ensure_space(this);
2259 last_pc_ = pc_; 2258 last_pc_ = pc_;
2260 EMIT(0x66); 2259 EMIT(0x66);
2261 EMIT(0x0F); 2260 EMIT(0x0F);
2262 EMIT(0x54); 2261 EMIT(0x54);
2263 emit_sse_operand(dst, src); 2262 emit_sse_operand(dst, src);
2264 } 2263 }
2265 2264
2266 2265
2267 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 2266 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2268 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2267 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2269 EnsureSpace ensure_space(this); 2268 EnsureSpace ensure_space(this);
2270 last_pc_ = pc_; 2269 last_pc_ = pc_;
2271 EMIT(0x66); 2270 EMIT(0x66);
2272 EMIT(0x0F); 2271 EMIT(0x0F);
2273 EMIT(0x2E); 2272 EMIT(0x2E);
2274 emit_sse_operand(dst, src); 2273 emit_sse_operand(dst, src);
2275 } 2274 }
2276 2275
2277 2276
2278 void Assembler::movmskpd(Register dst, XMMRegister src) { 2277 void Assembler::movmskpd(Register dst, XMMRegister src) {
2279 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2278 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2280 EnsureSpace ensure_space(this); 2279 EnsureSpace ensure_space(this);
2281 last_pc_ = pc_; 2280 last_pc_ = pc_;
2282 EMIT(0x66); 2281 EMIT(0x66);
2283 EMIT(0x0F); 2282 EMIT(0x0F);
2284 EMIT(0x50); 2283 EMIT(0x50);
2285 emit_sse_operand(dst, src); 2284 emit_sse_operand(dst, src);
2286 } 2285 }
2287 2286
2288 2287
2289 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) { 2288 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2290 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2289 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2291 EnsureSpace ensure_space(this); 2290 EnsureSpace ensure_space(this);
2292 last_pc_ = pc_; 2291 last_pc_ = pc_;
2293 EMIT(0xF2); 2292 EMIT(0xF2);
2294 EMIT(0x0F); 2293 EMIT(0x0F);
2295 EMIT(0xC2); 2294 EMIT(0xC2);
2296 emit_sse_operand(dst, src); 2295 emit_sse_operand(dst, src);
2297 EMIT(1); // LT == 1 2296 EMIT(1); // LT == 1
2298 } 2297 }
2299 2298
2300 2299
2301 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 2300 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2302 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2301 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2303 EnsureSpace ensure_space(this); 2302 EnsureSpace ensure_space(this);
2304 last_pc_ = pc_; 2303 last_pc_ = pc_;
2305 EMIT(0x0F); 2304 EMIT(0x0F);
2306 EMIT(0x28); 2305 EMIT(0x28);
2307 emit_sse_operand(dst, src); 2306 emit_sse_operand(dst, src);
2308 } 2307 }
2309 2308
2310 2309
2311 void Assembler::movdqa(const Operand& dst, XMMRegister src) { 2310 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2312 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2311 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2313 EnsureSpace ensure_space(this); 2312 EnsureSpace ensure_space(this);
2314 last_pc_ = pc_; 2313 last_pc_ = pc_;
2315 EMIT(0x66); 2314 EMIT(0x66);
2316 EMIT(0x0F); 2315 EMIT(0x0F);
2317 EMIT(0x7F); 2316 EMIT(0x7F);
2318 emit_sse_operand(src, dst); 2317 emit_sse_operand(src, dst);
2319 } 2318 }
2320 2319
2321 2320
2322 void Assembler::movdqa(XMMRegister dst, const Operand& src) { 2321 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2323 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2322 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2324 EnsureSpace ensure_space(this); 2323 EnsureSpace ensure_space(this);
2325 last_pc_ = pc_; 2324 last_pc_ = pc_;
2326 EMIT(0x66); 2325 EMIT(0x66);
2327 EMIT(0x0F); 2326 EMIT(0x0F);
2328 EMIT(0x6F); 2327 EMIT(0x6F);
2329 emit_sse_operand(dst, src); 2328 emit_sse_operand(dst, src);
2330 } 2329 }
2331 2330
2332 2331
2333 void Assembler::movdqu(const Operand& dst, XMMRegister src ) { 2332 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2334 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2333 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2335 EnsureSpace ensure_space(this); 2334 EnsureSpace ensure_space(this);
2336 last_pc_ = pc_; 2335 last_pc_ = pc_;
2337 EMIT(0xF3); 2336 EMIT(0xF3);
2338 EMIT(0x0F); 2337 EMIT(0x0F);
2339 EMIT(0x7F); 2338 EMIT(0x7F);
2340 emit_sse_operand(src, dst); 2339 emit_sse_operand(src, dst);
2341 } 2340 }
2342 2341
2343 2342
2344 void Assembler::movdqu(XMMRegister dst, const Operand& src) { 2343 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2345 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2344 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2346 EnsureSpace ensure_space(this); 2345 EnsureSpace ensure_space(this);
2347 last_pc_ = pc_; 2346 last_pc_ = pc_;
2348 EMIT(0xF3); 2347 EMIT(0xF3);
2349 EMIT(0x0F); 2348 EMIT(0x0F);
2350 EMIT(0x6F); 2349 EMIT(0x6F);
2351 emit_sse_operand(dst, src); 2350 emit_sse_operand(dst, src);
2352 } 2351 }
2353 2352
2354 2353
2355 void Assembler::movntdqa(XMMRegister dst, const Operand& src) { 2354 void Assembler::movntdqa(XMMRegister dst, const Operand& src) {
2356 ASSERT(CpuFeatures::IsEnabled(SSE4_1)); 2355 ASSERT(isolate()->cpu_features()->IsEnabled(SSE4_1));
2357 EnsureSpace ensure_space(this); 2356 EnsureSpace ensure_space(this);
2358 last_pc_ = pc_; 2357 last_pc_ = pc_;
2359 EMIT(0x66); 2358 EMIT(0x66);
2360 EMIT(0x0F); 2359 EMIT(0x0F);
2361 EMIT(0x38); 2360 EMIT(0x38);
2362 EMIT(0x2A); 2361 EMIT(0x2A);
2363 emit_sse_operand(dst, src); 2362 emit_sse_operand(dst, src);
2364 } 2363 }
2365 2364
2366 2365
2367 void Assembler::movntdq(const Operand& dst, XMMRegister src) { 2366 void Assembler::movntdq(const Operand& dst, XMMRegister src) {
2368 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2367 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2369 EnsureSpace ensure_space(this); 2368 EnsureSpace ensure_space(this);
2370 last_pc_ = pc_; 2369 last_pc_ = pc_;
2371 EMIT(0x66); 2370 EMIT(0x66);
2372 EMIT(0x0F); 2371 EMIT(0x0F);
2373 EMIT(0xE7); 2372 EMIT(0xE7);
2374 emit_sse_operand(src, dst); 2373 emit_sse_operand(src, dst);
2375 } 2374 }
2376 2375
2377 2376
2378 void Assembler::prefetch(const Operand& src, int level) { 2377 void Assembler::prefetch(const Operand& src, int level) {
(...skipping 15 matching lines...) Expand all
2394 2393
2395 2394
2396 void Assembler::movdbl(const Operand& dst, XMMRegister src) { 2395 void Assembler::movdbl(const Operand& dst, XMMRegister src) {
2397 EnsureSpace ensure_space(this); 2396 EnsureSpace ensure_space(this);
2398 last_pc_ = pc_; 2397 last_pc_ = pc_;
2399 movsd(dst, src); 2398 movsd(dst, src);
2400 } 2399 }
2401 2400
2402 2401
2403 void Assembler::movsd(const Operand& dst, XMMRegister src ) { 2402 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2404 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2403 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2405 EnsureSpace ensure_space(this); 2404 EnsureSpace ensure_space(this);
2406 last_pc_ = pc_; 2405 last_pc_ = pc_;
2407 EMIT(0xF2); // double 2406 EMIT(0xF2); // double
2408 EMIT(0x0F); 2407 EMIT(0x0F);
2409 EMIT(0x11); // store 2408 EMIT(0x11); // store
2410 emit_sse_operand(src, dst); 2409 emit_sse_operand(src, dst);
2411 } 2410 }
2412 2411
2413 2412
2414 void Assembler::movsd(XMMRegister dst, const Operand& src) { 2413 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2415 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2414 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2416 EnsureSpace ensure_space(this); 2415 EnsureSpace ensure_space(this);
2417 last_pc_ = pc_; 2416 last_pc_ = pc_;
2418 EMIT(0xF2); // double 2417 EMIT(0xF2); // double
2419 EMIT(0x0F); 2418 EMIT(0x0F);
2420 EMIT(0x10); // load 2419 EMIT(0x10); // load
2421 emit_sse_operand(dst, src); 2420 emit_sse_operand(dst, src);
2422 } 2421 }
2423 2422
2424 2423
2425 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 2424 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2426 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2425 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2427 EnsureSpace ensure_space(this); 2426 EnsureSpace ensure_space(this);
2428 last_pc_ = pc_; 2427 last_pc_ = pc_;
2429 EMIT(0xF2); 2428 EMIT(0xF2);
2430 EMIT(0x0F); 2429 EMIT(0x0F);
2431 EMIT(0x10); 2430 EMIT(0x10);
2432 emit_sse_operand(dst, src); 2431 emit_sse_operand(dst, src);
2433 } 2432 }
2434 2433
2435 2434
2436 void Assembler::movss(const Operand& dst, XMMRegister src ) { 2435 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2437 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2436 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2438 EnsureSpace ensure_space(this); 2437 EnsureSpace ensure_space(this);
2439 last_pc_ = pc_; 2438 last_pc_ = pc_;
2440 EMIT(0xF3); // float 2439 EMIT(0xF3); // float
2441 EMIT(0x0F); 2440 EMIT(0x0F);
2442 EMIT(0x11); // store 2441 EMIT(0x11); // store
2443 emit_sse_operand(src, dst); 2442 emit_sse_operand(src, dst);
2444 } 2443 }
2445 2444
2446 2445
2447 void Assembler::movss(XMMRegister dst, const Operand& src) { 2446 void Assembler::movss(XMMRegister dst, const Operand& src) {
2448 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2447 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2449 EnsureSpace ensure_space(this); 2448 EnsureSpace ensure_space(this);
2450 last_pc_ = pc_; 2449 last_pc_ = pc_;
2451 EMIT(0xF3); // float 2450 EMIT(0xF3); // float
2452 EMIT(0x0F); 2451 EMIT(0x0F);
2453 EMIT(0x10); // load 2452 EMIT(0x10); // load
2454 emit_sse_operand(dst, src); 2453 emit_sse_operand(dst, src);
2455 } 2454 }
2456 2455
2457 2456
2458 void Assembler::movss(XMMRegister dst, XMMRegister src) { 2457 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2459 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2458 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2460 EnsureSpace ensure_space(this); 2459 EnsureSpace ensure_space(this);
2461 last_pc_ = pc_; 2460 last_pc_ = pc_;
2462 EMIT(0xF3); 2461 EMIT(0xF3);
2463 EMIT(0x0F); 2462 EMIT(0x0F);
2464 EMIT(0x10); 2463 EMIT(0x10);
2465 emit_sse_operand(dst, src); 2464 emit_sse_operand(dst, src);
2466 } 2465 }
2467 2466
2468 2467
2469 void Assembler::movd(XMMRegister dst, const Operand& src) { 2468 void Assembler::movd(XMMRegister dst, const Operand& src) {
2470 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2469 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2471 EnsureSpace ensure_space(this); 2470 EnsureSpace ensure_space(this);
2472 last_pc_ = pc_; 2471 last_pc_ = pc_;
2473 EMIT(0x66); 2472 EMIT(0x66);
2474 EMIT(0x0F); 2473 EMIT(0x0F);
2475 EMIT(0x6E); 2474 EMIT(0x6E);
2476 emit_sse_operand(dst, src); 2475 emit_sse_operand(dst, src);
2477 } 2476 }
2478 2477
2479 2478
2480 void Assembler::movd(const Operand& dst, XMMRegister src) { 2479 void Assembler::movd(const Operand& dst, XMMRegister src) {
2481 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2480 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2482 EnsureSpace ensure_space(this); 2481 EnsureSpace ensure_space(this);
2483 last_pc_ = pc_; 2482 last_pc_ = pc_;
2484 EMIT(0x66); 2483 EMIT(0x66);
2485 EMIT(0x0F); 2484 EMIT(0x0F);
2486 EMIT(0x7E); 2485 EMIT(0x7E);
2487 emit_sse_operand(src, dst); 2486 emit_sse_operand(src, dst);
2488 } 2487 }
2489 2488
2490 2489
2491 void Assembler::pand(XMMRegister dst, XMMRegister src) { 2490 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2492 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2491 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2493 EnsureSpace ensure_space(this); 2492 EnsureSpace ensure_space(this);
2494 last_pc_ = pc_; 2493 last_pc_ = pc_;
2495 EMIT(0x66); 2494 EMIT(0x66);
2496 EMIT(0x0F); 2495 EMIT(0x0F);
2497 EMIT(0xDB); 2496 EMIT(0xDB);
2498 emit_sse_operand(dst, src); 2497 emit_sse_operand(dst, src);
2499 } 2498 }
2500 2499
2501 2500
2502 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 2501 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2503 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2502 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2504 EnsureSpace ensure_space(this); 2503 EnsureSpace ensure_space(this);
2505 last_pc_ = pc_; 2504 last_pc_ = pc_;
2506 EMIT(0x66); 2505 EMIT(0x66);
2507 EMIT(0x0F); 2506 EMIT(0x0F);
2508 EMIT(0xEF); 2507 EMIT(0xEF);
2509 emit_sse_operand(dst, src); 2508 emit_sse_operand(dst, src);
2510 } 2509 }
2511 2510
2512 2511
2513 void Assembler::por(XMMRegister dst, XMMRegister src) { 2512 void Assembler::por(XMMRegister dst, XMMRegister src) {
2514 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2513 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2515 EnsureSpace ensure_space(this); 2514 EnsureSpace ensure_space(this);
2516 last_pc_ = pc_; 2515 last_pc_ = pc_;
2517 EMIT(0x66); 2516 EMIT(0x66);
2518 EMIT(0x0F); 2517 EMIT(0x0F);
2519 EMIT(0xEB); 2518 EMIT(0xEB);
2520 emit_sse_operand(dst, src); 2519 emit_sse_operand(dst, src);
2521 } 2520 }
2522 2521
2523 2522
2524 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 2523 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2525 ASSERT(CpuFeatures::IsEnabled(SSE4_1)); 2524 ASSERT(isolate()->cpu_features()->IsEnabled(SSE4_1));
2526 EnsureSpace ensure_space(this); 2525 EnsureSpace ensure_space(this);
2527 last_pc_ = pc_; 2526 last_pc_ = pc_;
2528 EMIT(0x66); 2527 EMIT(0x66);
2529 EMIT(0x0F); 2528 EMIT(0x0F);
2530 EMIT(0x38); 2529 EMIT(0x38);
2531 EMIT(0x17); 2530 EMIT(0x17);
2532 emit_sse_operand(dst, src); 2531 emit_sse_operand(dst, src);
2533 } 2532 }
2534 2533
2535 2534
2536 void Assembler::psllq(XMMRegister reg, int8_t shift) { 2535 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2537 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2536 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2538 EnsureSpace ensure_space(this); 2537 EnsureSpace ensure_space(this);
2539 last_pc_ = pc_; 2538 last_pc_ = pc_;
2540 EMIT(0x66); 2539 EMIT(0x66);
2541 EMIT(0x0F); 2540 EMIT(0x0F);
2542 EMIT(0x73); 2541 EMIT(0x73);
2543 emit_sse_operand(esi, reg); // esi == 6 2542 emit_sse_operand(esi, reg); // esi == 6
2544 EMIT(shift); 2543 EMIT(shift);
2545 } 2544 }
2546 2545
2547 2546
2548 void Assembler::psllq(XMMRegister dst, XMMRegister src) { 2547 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2549 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2548 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2550 EnsureSpace ensure_space(this); 2549 EnsureSpace ensure_space(this);
2551 last_pc_ = pc_; 2550 last_pc_ = pc_;
2552 EMIT(0x66); 2551 EMIT(0x66);
2553 EMIT(0x0F); 2552 EMIT(0x0F);
2554 EMIT(0xF3); 2553 EMIT(0xF3);
2555 emit_sse_operand(dst, src); 2554 emit_sse_operand(dst, src);
2556 } 2555 }
2557 2556
2558 2557
2559 void Assembler::psrlq(XMMRegister reg, int8_t shift) { 2558 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2560 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2559 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2561 EnsureSpace ensure_space(this); 2560 EnsureSpace ensure_space(this);
2562 last_pc_ = pc_; 2561 last_pc_ = pc_;
2563 EMIT(0x66); 2562 EMIT(0x66);
2564 EMIT(0x0F); 2563 EMIT(0x0F);
2565 EMIT(0x73); 2564 EMIT(0x73);
2566 emit_sse_operand(edx, reg); // edx == 2 2565 emit_sse_operand(edx, reg); // edx == 2
2567 EMIT(shift); 2566 EMIT(shift);
2568 } 2567 }
2569 2568
2570 2569
2571 void Assembler::psrlq(XMMRegister dst, XMMRegister src) { 2570 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2572 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2571 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2573 EnsureSpace ensure_space(this); 2572 EnsureSpace ensure_space(this);
2574 last_pc_ = pc_; 2573 last_pc_ = pc_;
2575 EMIT(0x66); 2574 EMIT(0x66);
2576 EMIT(0x0F); 2575 EMIT(0x0F);
2577 EMIT(0xD3); 2576 EMIT(0xD3);
2578 emit_sse_operand(dst, src); 2577 emit_sse_operand(dst, src);
2579 } 2578 }
2580 2579
2581 2580
2582 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int8_t shuffle) { 2581 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int8_t shuffle) {
2583 ASSERT(CpuFeatures::IsEnabled(SSE2)); 2582 ASSERT(isolate()->cpu_features()->IsEnabled(SSE2));
2584 EnsureSpace ensure_space(this); 2583 EnsureSpace ensure_space(this);
2585 last_pc_ = pc_; 2584 last_pc_ = pc_;
2586 EMIT(0x66); 2585 EMIT(0x66);
2587 EMIT(0x0F); 2586 EMIT(0x0F);
2588 EMIT(0x70); 2587 EMIT(0x70);
2589 emit_sse_operand(dst, src); 2588 emit_sse_operand(dst, src);
2590 EMIT(shuffle); 2589 EMIT(shuffle);
2591 } 2590 }
2592 2591
2593 2592
2594 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) { 2593 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2595 ASSERT(CpuFeatures::IsEnabled(SSE4_1)); 2594 ASSERT(isolate()->cpu_features()->IsEnabled(SSE4_1));
2596 EnsureSpace ensure_space(this); 2595 EnsureSpace ensure_space(this);
2597 last_pc_ = pc_; 2596 last_pc_ = pc_;
2598 EMIT(0x66); 2597 EMIT(0x66);
2599 EMIT(0x0F); 2598 EMIT(0x0F);
2600 EMIT(0x3A); 2599 EMIT(0x3A);
2601 EMIT(0x16); 2600 EMIT(0x16);
2602 emit_sse_operand(src, dst); 2601 emit_sse_operand(src, dst);
2603 EMIT(offset); 2602 EMIT(offset);
2604 } 2603 }
2605 2604
2606 2605
2607 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) { 2606 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2608 ASSERT(CpuFeatures::IsEnabled(SSE4_1)); 2607 ASSERT(isolate()->cpu_features()->IsEnabled(SSE4_1));
2609 EnsureSpace ensure_space(this); 2608 EnsureSpace ensure_space(this);
2610 last_pc_ = pc_; 2609 last_pc_ = pc_;
2611 EMIT(0x66); 2610 EMIT(0x66);
2612 EMIT(0x0F); 2611 EMIT(0x0F);
2613 EMIT(0x3A); 2612 EMIT(0x3A);
2614 EMIT(0x22); 2613 EMIT(0x22);
2615 emit_sse_operand(dst, src); 2614 emit_sse_operand(dst, src);
2616 EMIT(offset); 2615 EMIT(offset);
2617 } 2616 }
2618 2617
(...skipping 218 matching lines...) Expand 10 before | Expand all | Expand 10 after
2837 fprintf(coverage_log, "%s\n", file_line); 2836 fprintf(coverage_log, "%s\n", file_line);
2838 fflush(coverage_log); 2837 fflush(coverage_log);
2839 } 2838 }
2840 } 2839 }
2841 2840
2842 #endif 2841 #endif
2843 2842
2844 } } // namespace v8::internal 2843 } } // namespace v8::internal
2845 2844
2846 #endif // V8_TARGET_ARCH_IA32 2845 #endif // V8_TARGET_ARCH_IA32
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