| Index: third_party/zlib/x86.c
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| diff --git a/third_party/zlib/x86.c b/third_party/zlib/x86.c
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| new file mode 100644
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| index 0000000000000000000000000000000000000000..35ec51624afd850ee70864636d4198685106f245
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| --- /dev/null
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| +++ b/third_party/zlib/x86.c
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| @@ -0,0 +1,112 @@
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| +/*
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| + * x86 feature check
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| + *
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| + * Copyright (C) 2013 Intel Corporation. All rights reserved.
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| + * Author:
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| + *  Jim Kukunas
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| + * 
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| + * For conditions of distribution and use, see copyright notice in zlib.h
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| + */
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| +
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| +#include "x86.h"
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| +
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| +int x86_cpu_enable_simd;
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| +
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| +#ifndef _MSC_VER
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| +#include <pthread.h>
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| +
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| +pthread_once_t cpu_check_inited_once = PTHREAD_ONCE_INIT;
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| +static void _x86_check_features(void);
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| +
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| +void x86_check_features(void)
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| +{
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| +  pthread_once(&cpu_check_inited_once, _x86_check_features);
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| +}
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| +
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| +static void _x86_check_features(void)
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| +{
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| +    int x86_cpu_has_sse2;
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| +    int x86_cpu_has_sse42;
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| +    int x86_cpu_has_pclmulqdq;
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| +    unsigned eax, ebx, ecx, edx;
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| +
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| +    eax = 1;
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| +#ifdef __i386__
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| +    __asm__ __volatile__ (
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| +        "xchg %%ebx, %1\n\t"
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| +        "cpuid\n\t"
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| +        "xchg %1, %%ebx\n\t"
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| +    : "+a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx)
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| +    );
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| +#else
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| +    __asm__ __volatile__ (
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| +        "cpuid\n\t"
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| +    : "+a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
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| +    );
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| +#endif  /* (__i386__) */
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| +
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| +    x86_cpu_has_sse2 = edx & 0x4000000;
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| +    x86_cpu_has_sse42 = ecx & 0x100000;
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| +    x86_cpu_has_pclmulqdq = ecx & 0x2;
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| +
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| +    x86_cpu_enable_simd = x86_cpu_has_sse2 &&
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| +                          x86_cpu_has_sse42 &&
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| +                          x86_cpu_has_pclmulqdq;
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| +}
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| +#else
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| +#include <intrin.h>
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| +#include <windows.h>
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| +#include <stdint.h>
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| +
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| +static volatile int32_t once_control = 0;
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| +static void _x86_check_features(void);
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| +static int fake_pthread_once(volatile int32_t *once_control,
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| +                             void (*init_routine)(void));
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| +
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| +void x86_check_features(void)
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| +{
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| +    fake_pthread_once(&once_control, _x86_check_features);
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| +}
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| +
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| +/* Copied from "perftools_pthread_once" in tcmalloc */
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| +static int fake_pthread_once(volatile int32_t *once_control,
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| +                             void (*init_routine)(void)) {
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| +    // Try for a fast path first. Note: this should be an acquire semantics read
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| +    // It is on x86 and x64, where Windows runs.
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| +    if (*once_control != 1) {
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| +        while (1) {
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| +            switch (InterlockedCompareExchange(once_control, 2, 0)) {
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| +                case 0:
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| +                    init_routine();
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| +                    InterlockedExchange(once_control, 1);
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| +                    return 0;
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| +                case 1:
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| +                    // The initializer has already been executed
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| +                    return 0;
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| +                default:
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| +                    // The initializer is being processed by another thread
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| +                    SwitchToThread();
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| +            }
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| +        }
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| +    }
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| +    return 0;
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| +}
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| +
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| +static void _x86_check_features(void)
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| +{
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| +    int x86_cpu_has_sse2;
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| +    int x86_cpu_has_sse42;
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| +    int x86_cpu_has_pclmulqdq;
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| +    int regs[4];
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| +
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| +    __cpuid(regs, 1);
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| +
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| +    x86_cpu_has_sse2 = regs[3] & 0x4000000;
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| +    x86_cpu_has_sse42= regs[2] & 0x100000;
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| +    x86_cpu_has_pclmulqdq = regs[2] & 0x2;
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| +
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| +    x86_cpu_enable_simd = x86_cpu_has_sse2 &&
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| +                          x86_cpu_has_sse42 &&
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| +                          x86_cpu_has_pclmulqdq;
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| +}
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| +#endif  /* _MSC_VER */
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| 
 |